648 lines
23 KiB
C++
648 lines
23 KiB
C++
//===- CodeGenSchedule.h - Scheduling Machine Models ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines structures to encapsulate the machine model as described in
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// the target description.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H
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#define LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/SetTheory.h"
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namespace llvm {
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class CodeGenTarget;
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class CodeGenSchedModels;
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class CodeGenInstruction;
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class CodeGenRegisterClass;
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using RecVec = std::vector<Record*>;
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using RecIter = std::vector<Record*>::const_iterator;
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using IdxVec = std::vector<unsigned>;
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using IdxIter = std::vector<unsigned>::const_iterator;
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/// We have two kinds of SchedReadWrites. Explicitly defined and inferred
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/// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
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/// may not be empty. TheDef is null for inferred sequences, and Sequence must
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/// be nonempty.
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///
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/// IsVariadic controls whether the variants are expanded into multiple operands
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/// or a sequence of writes on one operand.
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struct CodeGenSchedRW {
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unsigned Index;
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std::string Name;
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Record *TheDef;
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bool IsRead;
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bool IsAlias;
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bool HasVariants;
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bool IsVariadic;
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bool IsSequence;
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IdxVec Sequence;
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RecVec Aliases;
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CodeGenSchedRW()
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: Index(0), TheDef(nullptr), IsRead(false), IsAlias(false),
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HasVariants(false), IsVariadic(false), IsSequence(false) {}
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CodeGenSchedRW(unsigned Idx, Record *Def)
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: Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
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Name = Def->getName();
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IsRead = Def->isSubClassOf("SchedRead");
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HasVariants = Def->isSubClassOf("SchedVariant");
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if (HasVariants)
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IsVariadic = Def->getValueAsBit("Variadic");
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// Read records don't currently have sequences, but it can be easily
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// added. Note that implicit Reads (from ReadVariant) may have a Sequence
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// (but no record).
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IsSequence = Def->isSubClassOf("WriteSequence");
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}
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CodeGenSchedRW(unsigned Idx, bool Read, ArrayRef<unsigned> Seq,
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const std::string &Name)
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: Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false),
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HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) {
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assert(Sequence.size() > 1 && "implied sequence needs >1 RWs");
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}
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bool isValid() const {
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assert((!HasVariants || TheDef) && "Variant write needs record def");
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assert((!IsVariadic || HasVariants) && "Variadic write needs variants");
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assert((!IsSequence || !HasVariants) && "Sequence can't have variant");
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assert((!IsSequence || !Sequence.empty()) && "Sequence should be nonempty");
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assert((!IsAlias || Aliases.empty()) && "Alias cannot have aliases");
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return TheDef || !Sequence.empty();
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}
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#ifndef NDEBUG
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void dump() const;
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#endif
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};
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/// Represent a transition between SchedClasses induced by SchedVariant.
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struct CodeGenSchedTransition {
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unsigned ToClassIdx;
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IdxVec ProcIndices;
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RecVec PredTerm;
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};
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/// Scheduling class.
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///
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/// Each instruction description will be mapped to a scheduling class. There are
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/// four types of classes:
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///
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/// 1) An explicitly defined itinerary class with ItinClassDef set.
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/// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor.
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///
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/// 2) An implied class with a list of SchedWrites and SchedReads that are
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/// defined in an instruction definition and which are common across all
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/// subtargets. ProcIndices contains 0 for any processor.
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///
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/// 3) An implied class with a list of InstRW records that map instructions to
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/// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
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/// instructions to this class. ProcIndices contains all the processors that
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/// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
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/// still be defined for processors with no InstRW entry.
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///
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/// 4) An inferred class represents a variant of another class that may be
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/// resolved at runtime. ProcIndices contains the set of processors that may
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/// require the class. ProcIndices are propagated through SchedClasses as
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/// variants are expanded. Multiple SchedClasses may be inferred from an
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/// itinerary class. Each inherits the processor index from the ItinRW record
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/// that mapped the itinerary class to the variant Writes or Reads.
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struct CodeGenSchedClass {
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unsigned Index;
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std::string Name;
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Record *ItinClassDef;
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IdxVec Writes;
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IdxVec Reads;
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// Sorted list of ProcIdx, where ProcIdx==0 implies any processor.
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IdxVec ProcIndices;
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std::vector<CodeGenSchedTransition> Transitions;
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// InstRW records associated with this class. These records may refer to an
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// Instruction no longer mapped to this class by InstrClassMap. These
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// Instructions should be ignored by this class because they have been split
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// off to join another inferred class.
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RecVec InstRWs;
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CodeGenSchedClass(unsigned Index, std::string Name, Record *ItinClassDef)
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: Index(Index), Name(std::move(Name)), ItinClassDef(ItinClassDef) {}
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bool isKeyEqual(Record *IC, ArrayRef<unsigned> W,
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ArrayRef<unsigned> R) const {
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return ItinClassDef == IC && makeArrayRef(Writes) == W &&
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makeArrayRef(Reads) == R;
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}
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// Is this class generated from a variants if existing classes? Instructions
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// are never mapped directly to inferred scheduling classes.
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bool isInferred() const { return !ItinClassDef; }
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#ifndef NDEBUG
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void dump(const CodeGenSchedModels *SchedModels) const;
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#endif
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};
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/// Represent the cost of allocating a register of register class RCDef.
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///
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/// The cost of allocating a register is equivalent to the number of physical
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/// registers used by the register renamer. Register costs are defined at
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/// register class granularity.
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struct CodeGenRegisterCost {
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Record *RCDef;
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unsigned Cost;
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bool AllowMoveElimination;
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CodeGenRegisterCost(Record *RC, unsigned RegisterCost, bool AllowMoveElim = false)
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: RCDef(RC), Cost(RegisterCost), AllowMoveElimination(AllowMoveElim) {}
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CodeGenRegisterCost(const CodeGenRegisterCost &) = default;
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CodeGenRegisterCost &operator=(const CodeGenRegisterCost &) = delete;
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};
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/// A processor register file.
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///
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/// This class describes a processor register file. Register file information is
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/// currently consumed by external tools like llvm-mca to predict dispatch
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/// stalls due to register pressure.
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struct CodeGenRegisterFile {
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std::string Name;
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Record *RegisterFileDef;
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unsigned MaxMovesEliminatedPerCycle;
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bool AllowZeroMoveEliminationOnly;
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unsigned NumPhysRegs;
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std::vector<CodeGenRegisterCost> Costs;
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CodeGenRegisterFile(StringRef name, Record *def, unsigned MaxMoveElimPerCy = 0,
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bool AllowZeroMoveElimOnly = false)
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: Name(name), RegisterFileDef(def),
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MaxMovesEliminatedPerCycle(MaxMoveElimPerCy),
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AllowZeroMoveEliminationOnly(AllowZeroMoveElimOnly),
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NumPhysRegs(0) {}
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bool hasDefaultCosts() const { return Costs.empty(); }
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};
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// Processor model.
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//
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// ModelName is a unique name used to name an instantiation of MCSchedModel.
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//
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// ModelDef is NULL for inferred Models. This happens when a processor defines
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// an itinerary but no machine model. If the processor defines neither a machine
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// model nor itinerary, then ModelDef remains pointing to NoModel. NoModel has
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// the special "NoModel" field set to true.
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//
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// ItinsDef always points to a valid record definition, but may point to the
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// default NoItineraries. NoItineraries has an empty list of InstrItinData
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// records.
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//
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// ItinDefList orders this processor's InstrItinData records by SchedClass idx.
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struct CodeGenProcModel {
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unsigned Index;
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std::string ModelName;
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Record *ModelDef;
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Record *ItinsDef;
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// Derived members...
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// Array of InstrItinData records indexed by a CodeGenSchedClass index.
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// This list is empty if the Processor has no value for Itineraries.
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// Initialized by collectProcItins().
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RecVec ItinDefList;
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// Map itinerary classes to per-operand resources.
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// This list is empty if no ItinRW refers to this Processor.
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RecVec ItinRWDefs;
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// List of unsupported feature.
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// This list is empty if the Processor has no UnsupportedFeatures.
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RecVec UnsupportedFeaturesDefs;
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// All read/write resources associated with this processor.
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RecVec WriteResDefs;
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RecVec ReadAdvanceDefs;
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// Per-operand machine model resources associated with this processor.
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RecVec ProcResourceDefs;
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// List of Register Files.
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std::vector<CodeGenRegisterFile> RegisterFiles;
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// Optional Retire Control Unit definition.
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Record *RetireControlUnit;
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// Load/Store queue descriptors.
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Record *LoadQueue;
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Record *StoreQueue;
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CodeGenProcModel(unsigned Idx, std::string Name, Record *MDef,
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Record *IDef) :
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Index(Idx), ModelName(std::move(Name)), ModelDef(MDef), ItinsDef(IDef),
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RetireControlUnit(nullptr), LoadQueue(nullptr), StoreQueue(nullptr) {}
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bool hasItineraries() const {
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return !ItinsDef->getValueAsListOfDefs("IID").empty();
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}
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bool hasInstrSchedModel() const {
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return !WriteResDefs.empty() || !ItinRWDefs.empty();
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}
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bool hasExtraProcessorInfo() const {
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return RetireControlUnit || LoadQueue || StoreQueue ||
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!RegisterFiles.empty();
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}
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unsigned getProcResourceIdx(Record *PRDef) const;
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bool isUnsupported(const CodeGenInstruction &Inst) const;
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#ifndef NDEBUG
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void dump() const;
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#endif
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};
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/// Used to correlate instructions to MCInstPredicates specified by
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/// InstructionEquivalentClass tablegen definitions.
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///
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/// Example: a XOR of a register with self, is a known zero-idiom for most
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/// X86 processors.
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///
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/// Each processor can use a (potentially different) InstructionEquivalenceClass
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/// definition to classify zero-idioms. That means, XORrr is likely to appear
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/// in more than one equivalence class (where each class definition is
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/// contributed by a different processor).
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///
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/// There is no guarantee that the same MCInstPredicate will be used to describe
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/// equivalence classes that identify XORrr as a zero-idiom.
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///
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/// To be more specific, the requirements for being a zero-idiom XORrr may be
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/// different for different processors.
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///
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/// Class PredicateInfo identifies a subset of processors that specify the same
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/// requirements (i.e. same MCInstPredicate and OperandMask) for an instruction
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/// opcode.
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///
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/// Back to the example. Field `ProcModelMask` will have one bit set for every
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/// processor model that sees XORrr as a zero-idiom, and that specifies the same
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/// set of constraints.
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///
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/// By construction, there can be multiple instances of PredicateInfo associated
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/// with a same instruction opcode. For example, different processors may define
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/// different constraints on the same opcode.
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///
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/// Field OperandMask can be used as an extra constraint.
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/// It may be used to describe conditions that appy only to a subset of the
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/// operands of a machine instruction, and the operands subset may not be the
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/// same for all processor models.
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struct PredicateInfo {
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llvm::APInt ProcModelMask; // A set of processor model indices.
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llvm::APInt OperandMask; // An operand mask.
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const Record *Predicate; // MCInstrPredicate definition.
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PredicateInfo(llvm::APInt CpuMask, llvm::APInt Operands, const Record *Pred)
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: ProcModelMask(CpuMask), OperandMask(Operands), Predicate(Pred) {}
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bool operator==(const PredicateInfo &Other) const {
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return ProcModelMask == Other.ProcModelMask &&
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OperandMask == Other.OperandMask && Predicate == Other.Predicate;
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}
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};
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/// A collection of PredicateInfo objects.
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///
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/// There is at least one OpcodeInfo object for every opcode specified by a
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/// TIPredicate definition.
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class OpcodeInfo {
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std::vector<PredicateInfo> Predicates;
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OpcodeInfo(const OpcodeInfo &Other) = delete;
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OpcodeInfo &operator=(const OpcodeInfo &Other) = delete;
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public:
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OpcodeInfo() = default;
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OpcodeInfo &operator=(OpcodeInfo &&Other) = default;
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OpcodeInfo(OpcodeInfo &&Other) = default;
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ArrayRef<PredicateInfo> getPredicates() const { return Predicates; }
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void addPredicateForProcModel(const llvm::APInt &CpuMask,
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const llvm::APInt &OperandMask,
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const Record *Predicate);
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};
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/// Used to group together tablegen instruction definitions that are subject
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/// to a same set of constraints (identified by an instance of OpcodeInfo).
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class OpcodeGroup {
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OpcodeInfo Info;
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std::vector<const Record *> Opcodes;
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OpcodeGroup(const OpcodeGroup &Other) = delete;
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OpcodeGroup &operator=(const OpcodeGroup &Other) = delete;
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public:
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OpcodeGroup(OpcodeInfo &&OpInfo) : Info(std::move(OpInfo)) {}
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OpcodeGroup(OpcodeGroup &&Other) = default;
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void addOpcode(const Record *Opcode) {
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assert(std::find(Opcodes.begin(), Opcodes.end(), Opcode) == Opcodes.end() &&
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"Opcode already in set!");
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Opcodes.push_back(Opcode);
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}
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ArrayRef<const Record *> getOpcodes() const { return Opcodes; }
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const OpcodeInfo &getOpcodeInfo() const { return Info; }
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};
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/// An STIPredicateFunction descriptor used by tablegen backends to
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/// auto-generate the body of a predicate function as a member of tablegen'd
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/// class XXXGenSubtargetInfo.
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class STIPredicateFunction {
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const Record *FunctionDeclaration;
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std::vector<const Record *> Definitions;
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std::vector<OpcodeGroup> Groups;
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STIPredicateFunction(const STIPredicateFunction &Other) = delete;
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STIPredicateFunction &operator=(const STIPredicateFunction &Other) = delete;
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public:
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STIPredicateFunction(const Record *Rec) : FunctionDeclaration(Rec) {}
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STIPredicateFunction(STIPredicateFunction &&Other) = default;
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bool isCompatibleWith(const STIPredicateFunction &Other) const {
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return FunctionDeclaration == Other.FunctionDeclaration;
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}
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void addDefinition(const Record *Def) { Definitions.push_back(Def); }
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void addOpcode(const Record *OpcodeRec, OpcodeInfo &&Info) {
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if (Groups.empty() ||
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Groups.back().getOpcodeInfo().getPredicates() != Info.getPredicates())
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Groups.emplace_back(std::move(Info));
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Groups.back().addOpcode(OpcodeRec);
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}
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StringRef getName() const {
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return FunctionDeclaration->getValueAsString("Name");
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}
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const Record *getDefaultReturnPredicate() const {
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return FunctionDeclaration->getValueAsDef("DefaultReturnValue");
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}
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const Record *getDeclaration() const { return FunctionDeclaration; }
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ArrayRef<const Record *> getDefinitions() const { return Definitions; }
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ArrayRef<OpcodeGroup> getGroups() const { return Groups; }
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};
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/// Top level container for machine model data.
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class CodeGenSchedModels {
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RecordKeeper &Records;
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const CodeGenTarget &Target;
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// Map dag expressions to Instruction lists.
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SetTheory Sets;
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// List of unique processor models.
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std::vector<CodeGenProcModel> ProcModels;
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// Map Processor's MachineModel or ProcItin to a CodeGenProcModel index.
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using ProcModelMapTy = DenseMap<Record*, unsigned>;
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ProcModelMapTy ProcModelMap;
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// Per-operand SchedReadWrite types.
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std::vector<CodeGenSchedRW> SchedWrites;
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std::vector<CodeGenSchedRW> SchedReads;
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// List of unique SchedClasses.
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std::vector<CodeGenSchedClass> SchedClasses;
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// Any inferred SchedClass has an index greater than NumInstrSchedClassses.
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unsigned NumInstrSchedClasses;
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RecVec ProcResourceDefs;
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RecVec ProcResGroups;
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// Map each instruction to its unique SchedClass index considering the
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// combination of it's itinerary class, SchedRW list, and InstRW records.
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using InstClassMapTy = DenseMap<Record*, unsigned>;
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InstClassMapTy InstrClassMap;
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std::vector<STIPredicateFunction> STIPredicates;
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public:
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CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
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// iterator access to the scheduling classes.
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using class_iterator = std::vector<CodeGenSchedClass>::iterator;
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using const_class_iterator = std::vector<CodeGenSchedClass>::const_iterator;
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class_iterator classes_begin() { return SchedClasses.begin(); }
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const_class_iterator classes_begin() const { return SchedClasses.begin(); }
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class_iterator classes_end() { return SchedClasses.end(); }
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const_class_iterator classes_end() const { return SchedClasses.end(); }
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iterator_range<class_iterator> classes() {
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return make_range(classes_begin(), classes_end());
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}
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iterator_range<const_class_iterator> classes() const {
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return make_range(classes_begin(), classes_end());
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}
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iterator_range<class_iterator> explicit_classes() {
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return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses);
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}
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iterator_range<const_class_iterator> explicit_classes() const {
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return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses);
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}
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Record *getModelOrItinDef(Record *ProcDef) const {
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Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
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Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");
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if (!ItinsDef->getValueAsListOfDefs("IID").empty()) {
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assert(ModelDef->getValueAsBit("NoModel")
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&& "Itineraries must be defined within SchedMachineModel");
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return ItinsDef;
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}
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return ModelDef;
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}
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const CodeGenProcModel &getModelForProc(Record *ProcDef) const {
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Record *ModelDef = getModelOrItinDef(ProcDef);
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ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
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assert(I != ProcModelMap.end() && "missing machine model");
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return ProcModels[I->second];
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}
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CodeGenProcModel &getProcModel(Record *ModelDef) {
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ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
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assert(I != ProcModelMap.end() && "missing machine model");
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return ProcModels[I->second];
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}
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const CodeGenProcModel &getProcModel(Record *ModelDef) const {
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return const_cast<CodeGenSchedModels*>(this)->getProcModel(ModelDef);
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}
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// Iterate over the unique processor models.
|
|
using ProcIter = std::vector<CodeGenProcModel>::const_iterator;
|
|
ProcIter procModelBegin() const { return ProcModels.begin(); }
|
|
ProcIter procModelEnd() const { return ProcModels.end(); }
|
|
ArrayRef<CodeGenProcModel> procModels() const { return ProcModels; }
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|
|
|
// Return true if any processors have itineraries.
|
|
bool hasItineraries() const;
|
|
|
|
// Get a SchedWrite from its index.
|
|
const CodeGenSchedRW &getSchedWrite(unsigned Idx) const {
|
|
assert(Idx < SchedWrites.size() && "bad SchedWrite index");
|
|
assert(SchedWrites[Idx].isValid() && "invalid SchedWrite");
|
|
return SchedWrites[Idx];
|
|
}
|
|
// Get a SchedWrite from its index.
|
|
const CodeGenSchedRW &getSchedRead(unsigned Idx) const {
|
|
assert(Idx < SchedReads.size() && "bad SchedRead index");
|
|
assert(SchedReads[Idx].isValid() && "invalid SchedRead");
|
|
return SchedReads[Idx];
|
|
}
|
|
|
|
const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const {
|
|
return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx);
|
|
}
|
|
CodeGenSchedRW &getSchedRW(Record *Def) {
|
|
bool IsRead = Def->isSubClassOf("SchedRead");
|
|
unsigned Idx = getSchedRWIdx(Def, IsRead);
|
|
return const_cast<CodeGenSchedRW&>(
|
|
IsRead ? getSchedRead(Idx) : getSchedWrite(Idx));
|
|
}
|
|
const CodeGenSchedRW &getSchedRW(Record *Def) const {
|
|
return const_cast<CodeGenSchedModels&>(*this).getSchedRW(Def);
|
|
}
|
|
|
|
unsigned getSchedRWIdx(const Record *Def, bool IsRead) const;
|
|
|
|
// Return true if the given write record is referenced by a ReadAdvance.
|
|
bool hasReadOfWrite(Record *WriteDef) const;
|
|
|
|
// Get a SchedClass from its index.
|
|
CodeGenSchedClass &getSchedClass(unsigned Idx) {
|
|
assert(Idx < SchedClasses.size() && "bad SchedClass index");
|
|
return SchedClasses[Idx];
|
|
}
|
|
const CodeGenSchedClass &getSchedClass(unsigned Idx) const {
|
|
assert(Idx < SchedClasses.size() && "bad SchedClass index");
|
|
return SchedClasses[Idx];
|
|
}
|
|
|
|
// Get the SchedClass index for an instruction. Instructions with no
|
|
// itinerary, no SchedReadWrites, and no InstrReadWrites references return 0
|
|
// for NoItinerary.
|
|
unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const;
|
|
|
|
using SchedClassIter = std::vector<CodeGenSchedClass>::const_iterator;
|
|
SchedClassIter schedClassBegin() const { return SchedClasses.begin(); }
|
|
SchedClassIter schedClassEnd() const { return SchedClasses.end(); }
|
|
ArrayRef<CodeGenSchedClass> schedClasses() const { return SchedClasses; }
|
|
|
|
unsigned numInstrSchedClasses() const { return NumInstrSchedClasses; }
|
|
|
|
void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
|
|
void findRWs(const RecVec &RWDefs, IdxVec &RWs, bool IsRead) const;
|
|
void expandRWSequence(unsigned RWIdx, IdxVec &RWSeq, bool IsRead) const;
|
|
void expandRWSeqForProc(unsigned RWIdx, IdxVec &RWSeq, bool IsRead,
|
|
const CodeGenProcModel &ProcModel) const;
|
|
|
|
unsigned addSchedClass(Record *ItinDef, ArrayRef<unsigned> OperWrites,
|
|
ArrayRef<unsigned> OperReads,
|
|
ArrayRef<unsigned> ProcIndices);
|
|
|
|
unsigned findOrInsertRW(ArrayRef<unsigned> Seq, bool IsRead);
|
|
|
|
Record *findProcResUnits(Record *ProcResKind, const CodeGenProcModel &PM,
|
|
ArrayRef<SMLoc> Loc) const;
|
|
|
|
ArrayRef<STIPredicateFunction> getSTIPredicates() const {
|
|
return STIPredicates;
|
|
}
|
|
private:
|
|
void collectProcModels();
|
|
|
|
// Initialize a new processor model if it is unique.
|
|
void addProcModel(Record *ProcDef);
|
|
|
|
void collectSchedRW();
|
|
|
|
std::string genRWName(ArrayRef<unsigned> Seq, bool IsRead);
|
|
unsigned findRWForSequence(ArrayRef<unsigned> Seq, bool IsRead);
|
|
|
|
void collectSchedClasses();
|
|
|
|
void collectRetireControlUnits();
|
|
|
|
void collectRegisterFiles();
|
|
|
|
void collectOptionalProcessorInfo();
|
|
|
|
std::string createSchedClassName(Record *ItinClassDef,
|
|
ArrayRef<unsigned> OperWrites,
|
|
ArrayRef<unsigned> OperReads);
|
|
std::string createSchedClassName(const RecVec &InstDefs);
|
|
void createInstRWClass(Record *InstRWDef);
|
|
|
|
void collectProcItins();
|
|
|
|
void collectProcItinRW();
|
|
|
|
void collectProcUnsupportedFeatures();
|
|
|
|
void inferSchedClasses();
|
|
|
|
void checkMCInstPredicates() const;
|
|
|
|
void checkSTIPredicates() const;
|
|
|
|
void collectSTIPredicates();
|
|
|
|
void collectLoadStoreQueueInfo();
|
|
|
|
void checkCompleteness();
|
|
|
|
void inferFromRW(ArrayRef<unsigned> OperWrites, ArrayRef<unsigned> OperReads,
|
|
unsigned FromClassIdx, ArrayRef<unsigned> ProcIndices);
|
|
void inferFromItinClass(Record *ItinClassDef, unsigned FromClassIdx);
|
|
void inferFromInstRWs(unsigned SCIdx);
|
|
|
|
bool hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM);
|
|
void verifyProcResourceGroups(CodeGenProcModel &PM);
|
|
|
|
void collectProcResources();
|
|
|
|
void collectItinProcResources(Record *ItinClassDef);
|
|
|
|
void collectRWResources(unsigned RWIdx, bool IsRead,
|
|
ArrayRef<unsigned> ProcIndices);
|
|
|
|
void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
|
|
ArrayRef<unsigned> ProcIndices);
|
|
|
|
void addProcResource(Record *ProcResourceKind, CodeGenProcModel &PM,
|
|
ArrayRef<SMLoc> Loc);
|
|
|
|
void addWriteRes(Record *ProcWriteResDef, unsigned PIdx);
|
|
|
|
void addReadAdvance(Record *ProcReadAdvanceDef, unsigned PIdx);
|
|
};
|
|
|
|
} // namespace llvm
|
|
|
|
#endif
|