d3514c2942
This code implements the "kpssv2" flavour of CPU regulator/clock gating in Linux. It's used by at least the ipq4018/4019 to power on and off CPU cores. This is based on the Linux implementation - the register definitions and values are from Linux and I've reverse engineered the sequencing requirements. The MP bring-up is: * set cold boot address via an SCM call - this is the address used by the bootloader/TZ firmware to jump to when the CPUs boot * power down the LDO feeding the CPU core and wait for it to settle * program in the right set of LDO and power tree configuration for the CPU regulator to power up the core. Unfortunately these are magic numbers that I've not found documented anywhere. * (I think) power up the shared L2 cache connect if it isn't. * Clamp the power into the core down; put the core into reset * Unclamp the power rail; release reset; and then set the core to boot. The MP core will then boot the bootloader/TZ firmware and then will wait until an incoming interrupt kicks it to start @ mpentry. Tested: * IPQ4019, 4 CPUs Release APs CPU(3) applied BP hardening: not necessary CPU(1) applied BP hardening: not necessary CPU(2) applied BP hardening: not necessary Reviewed by: andrew, manu, imp Differential Revision: https://reviews.freebsd.org/D32723
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