3c1f73b18d
It is possible that wrmsr in amd_stop_pmc() causes an overflow in a counter that it disables. In that case a non-maskable interrupt is generated. The interrupt handler code was written in such a way that it would re-enable the counter. That would lead to an unexpected interrupt later on. This problem was easy to reproduce with $ pmcstat -T -P instructions -t $pid if the target process is sufficiently busy and there are context switches from time to time. There would be a lot of interrupts to "race" with amd_stop_pmc() called during the context switches. The problem affected only AMD processors. While there, trace whether amd_intr() claimed an interrupt. Reviewed by: jhb MFC after: 2 weeks |
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| .. | ||
| hwpmc_amd.c | ||
| hwpmc_amd.h | ||
| hwpmc_arm64_md.c | ||
| hwpmc_arm64.c | ||
| hwpmc_arm64.h | ||
| hwpmc_arm.c | ||
| hwpmc_armv7.c | ||
| hwpmc_armv7.h | ||
| hwpmc_core.c | ||
| hwpmc_core.h | ||
| hwpmc_e500.c | ||
| hwpmc_intel.c | ||
| hwpmc_logging.c | ||
| hwpmc_mips24k.c | ||
| hwpmc_mips74k.c | ||
| hwpmc_mips.c | ||
| hwpmc_mod.c | ||
| hwpmc_mpc7xxx.c | ||
| hwpmc_octeon.c | ||
| hwpmc_pentium.c | ||
| hwpmc_pentium.h | ||
| hwpmc_piv.c | ||
| hwpmc_piv.h | ||
| hwpmc_powerpc.c | ||
| hwpmc_powerpc.h | ||
| hwpmc_ppc970.c | ||
| hwpmc_ppro.c | ||
| hwpmc_ppro.h | ||
| hwpmc_riscv.h | ||
| hwpmc_soft.c | ||
| hwpmc_soft.h | ||
| hwpmc_sparc64.c | ||
| hwpmc_tsc.c | ||
| hwpmc_tsc.h | ||
| hwpmc_uncore.c | ||
| hwpmc_uncore.h | ||
| hwpmc_x86.c | ||
| hwpmc_xscale.c | ||
| hwpmc_xscale.h | ||
| pmc_events.h | ||