824cfb4729
- Do not rely on U-Boot for clocks configuration, enable and set frequencies in the driver's attach method. - Adjust MAC settings according to detected linespeed on RK3399 and RK3328. - Add support for RMII PHY mode on RK3328. Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D26006
626 lines
17 KiB
C
626 lines
17 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <machine/bus.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/dwc/if_dwc.h>
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#include <dev/dwc/if_dwcvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/extres/regulator/regulator.h>
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#include <dev/extres/syscon/syscon.h>
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#include "if_dwc_if.h"
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#include "syscon_if.h"
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#define RK3328_GRF_MAC_CON0 0x0900
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#define MAC_CON0_GMAC2IO_TX_DL_CFG_MASK 0x7F
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#define MAC_CON0_GMAC2IO_TX_DL_CFG_SHIFT 0
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#define MAC_CON0_GMAC2IO_RX_DL_CFG_MASK 0x7F
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#define MAC_CON0_GMAC2IO_RX_DL_CFG_SHIFT 7
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#define RK3328_GRF_MAC_CON1 0x0904
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#define MAC_CON1_GMAC2IO_GMAC_TXCLK_DLY_ENA (1 << 0)
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#define MAC_CON1_GMAC2IO_GMAC_RXCLK_DLY_ENA (1 << 1)
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#define MAC_CON1_GMAC2IO_GMII_CLK_SEL_MASK (3 << 11)
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#define MAC_CON1_GMAC2IO_GMII_CLK_SEL_125 (0 << 11)
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#define MAC_CON1_GMAC2IO_GMII_CLK_SEL_25 (3 << 11)
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#define MAC_CON1_GMAC2IO_GMII_CLK_SEL_2_5 (2 << 11)
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#define MAC_CON1_GMAC2IO_RMII_MODE_MASK (1 << 9)
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#define MAC_CON1_GMAC2IO_RMII_MODE (1 << 9)
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#define MAC_CON1_GMAC2IO_INTF_SEL_MASK (7 << 4)
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#define MAC_CON1_GMAC2IO_INTF_RMII (4 << 4)
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#define MAC_CON1_GMAC2IO_INTF_RGMII (1 << 4)
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#define MAC_CON1_GMAC2IO_RMII_CLK_SEL_MASK (1 << 7)
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#define MAC_CON1_GMAC2IO_RMII_CLK_SEL_25 (1 << 7)
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#define MAC_CON1_GMAC2IO_RMII_CLK_SEL_2_5 (0 << 7)
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#define MAC_CON1_GMAC2IO_MAC_SPEED_MASK (1 << 2)
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#define MAC_CON1_GMAC2IO_MAC_SPEED_100 (1 << 2)
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#define MAC_CON1_GMAC2IO_MAC_SPEED_10 (0 << 2)
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#define RK3328_GRF_MAC_CON2 0x0908
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#define RK3328_GRF_MACPHY_CON0 0x0B00
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#define MACPHY_CON0_CLK_50M_MASK (1 << 14)
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#define MACPHY_CON0_CLK_50M (1 << 14)
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#define MACPHY_CON0_RMII_MODE_MASK (3 << 6)
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#define MACPHY_CON0_RMII_MODE (1 << 6)
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#define RK3328_GRF_MACPHY_CON1 0x0B04
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#define MACPHY_CON1_RMII_MODE_MASK (1 << 9)
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#define MACPHY_CON1_RMII_MODE (1 << 9)
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#define RK3328_GRF_MACPHY_CON2 0x0B08
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#define RK3328_GRF_MACPHY_CON3 0x0B0C
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#define RK3328_GRF_MACPHY_STATUS 0x0B10
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#define RK3399_GRF_SOC_CON5 0xc214
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#define SOC_CON5_GMAC_CLK_SEL_MASK (3 << 4)
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#define SOC_CON5_GMAC_CLK_SEL_125 (0 << 4)
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#define SOC_CON5_GMAC_CLK_SEL_25 (3 << 4)
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#define SOC_CON5_GMAC_CLK_SEL_2_5 (2 << 4)
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#define RK3399_GRF_SOC_CON6 0xc218
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#define SOC_CON6_GMAC_TXCLK_DLY_ENA (1 << 7)
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#define SOC_CON6_TX_DL_CFG_MASK 0x7F
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#define SOC_CON6_TX_DL_CFG_SHIFT 0
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#define SOC_CON6_RX_DL_CFG_MASK 0x7F
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#define SOC_CON6_GMAC_RXCLK_DLY_ENA (1 << 15)
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#define SOC_CON6_RX_DL_CFG_SHIFT 8
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struct if_dwc_rk_softc;
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typedef void (*if_dwc_rk_set_delaysfn_t)(struct if_dwc_rk_softc *);
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typedef int (*if_dwc_rk_set_speedfn_t)(struct if_dwc_rk_softc *, int);
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typedef void (*if_dwc_rk_set_phy_modefn_t)(struct if_dwc_rk_softc *);
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typedef void (*if_dwc_rk_phy_powerupfn_t)(struct if_dwc_rk_softc *);
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struct if_dwc_rk_ops {
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if_dwc_rk_set_delaysfn_t set_delays;
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if_dwc_rk_set_speedfn_t set_speed;
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if_dwc_rk_set_phy_modefn_t set_phy_mode;
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if_dwc_rk_phy_powerupfn_t phy_powerup;
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};
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struct if_dwc_rk_softc {
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struct dwc_softc base;
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uint32_t tx_delay;
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uint32_t rx_delay;
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bool integrated_phy;
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bool clock_in;
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phandle_t phy_node;
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struct syscon *grf;
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struct if_dwc_rk_ops *ops;
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/* Common clocks */
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clk_t mac_clk_rx;
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clk_t mac_clk_tx;
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clk_t aclk_mac;
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clk_t pclk_mac;
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clk_t clk_stmmaceth;
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/* RMII clocks */
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clk_t clk_mac_ref;
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clk_t clk_mac_refout;
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/* PHY clock */
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clk_t clk_phy;
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};
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static void rk3328_set_delays(struct if_dwc_rk_softc *sc);
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static int rk3328_set_speed(struct if_dwc_rk_softc *sc, int speed);
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static void rk3328_set_phy_mode(struct if_dwc_rk_softc *sc);
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static void rk3328_phy_powerup(struct if_dwc_rk_softc *sc);
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static void rk3399_set_delays(struct if_dwc_rk_softc *sc);
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static int rk3399_set_speed(struct if_dwc_rk_softc *sc, int speed);
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static struct if_dwc_rk_ops rk3288_ops = {
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};
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static struct if_dwc_rk_ops rk3328_ops = {
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.set_delays = rk3328_set_delays,
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.set_speed = rk3328_set_speed,
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.set_phy_mode = rk3328_set_phy_mode,
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.phy_powerup = rk3328_phy_powerup,
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};
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static struct if_dwc_rk_ops rk3399_ops = {
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.set_delays = rk3399_set_delays,
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.set_speed = rk3399_set_speed,
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};
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static struct ofw_compat_data compat_data[] = {
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{"rockchip,rk3288-gmac", (uintptr_t)&rk3288_ops},
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{"rockchip,rk3328-gmac", (uintptr_t)&rk3328_ops},
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{"rockchip,rk3399-gmac", (uintptr_t)&rk3399_ops},
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{NULL, 0}
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};
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static void
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rk3328_set_delays(struct if_dwc_rk_softc *sc)
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{
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uint32_t reg;
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uint32_t tx, rx;
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if (sc->base.phy_mode != PHY_MODE_RGMII)
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return;
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reg = SYSCON_READ_4(sc->grf, RK3328_GRF_MAC_CON0);
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tx = ((reg >> MAC_CON0_GMAC2IO_TX_DL_CFG_SHIFT) & MAC_CON0_GMAC2IO_TX_DL_CFG_MASK);
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rx = ((reg >> MAC_CON0_GMAC2IO_RX_DL_CFG_SHIFT) & MAC_CON0_GMAC2IO_RX_DL_CFG_MASK);
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reg = SYSCON_READ_4(sc->grf, RK3328_GRF_MAC_CON1);
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if (bootverbose) {
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device_printf(sc->base.dev, "current delays settings: tx=%u(%s) rx=%u(%s)\n",
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tx, ((reg & MAC_CON1_GMAC2IO_GMAC_TXCLK_DLY_ENA) ? "enabled" : "disabled"),
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rx, ((reg & MAC_CON1_GMAC2IO_GMAC_RXCLK_DLY_ENA) ? "enabled" : "disabled"));
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device_printf(sc->base.dev, "setting new RK3328 RX/TX delays: %d/%d\n",
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sc->tx_delay, sc->rx_delay);
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}
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reg = (MAC_CON1_GMAC2IO_GMAC_TXCLK_DLY_ENA | MAC_CON1_GMAC2IO_GMAC_RXCLK_DLY_ENA) << 16;
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reg |= (MAC_CON1_GMAC2IO_GMAC_TXCLK_DLY_ENA | MAC_CON1_GMAC2IO_GMAC_RXCLK_DLY_ENA);
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SYSCON_WRITE_4(sc->grf, RK3328_GRF_MAC_CON1, reg);
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reg = 0xffff << 16;
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reg |= ((sc->tx_delay & MAC_CON0_GMAC2IO_TX_DL_CFG_MASK) <<
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MAC_CON0_GMAC2IO_TX_DL_CFG_SHIFT);
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reg |= ((sc->rx_delay & MAC_CON0_GMAC2IO_TX_DL_CFG_MASK) <<
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MAC_CON0_GMAC2IO_RX_DL_CFG_SHIFT);
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SYSCON_WRITE_4(sc->grf, RK3328_GRF_MAC_CON0, reg);
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}
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static int
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rk3328_set_speed(struct if_dwc_rk_softc *sc, int speed)
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{
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uint32_t reg;
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switch (sc->base.phy_mode) {
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case PHY_MODE_RGMII:
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switch (speed) {
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case IFM_1000_T:
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case IFM_1000_SX:
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reg = MAC_CON1_GMAC2IO_GMII_CLK_SEL_125;
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break;
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case IFM_100_TX:
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reg = MAC_CON1_GMAC2IO_GMII_CLK_SEL_25;
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break;
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case IFM_10_T:
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reg = MAC_CON1_GMAC2IO_GMII_CLK_SEL_2_5;
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break;
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default:
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device_printf(sc->base.dev, "unsupported RGMII media %u\n", speed);
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return (-1);
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}
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SYSCON_WRITE_4(sc->grf, RK3328_GRF_MAC_CON1,
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((MAC_CON1_GMAC2IO_GMII_CLK_SEL_MASK << 16) | reg));
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break;
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case PHY_MODE_RMII:
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switch (speed) {
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case IFM_100_TX:
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reg = MAC_CON1_GMAC2IO_RMII_CLK_SEL_25 |
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MAC_CON1_GMAC2IO_MAC_SPEED_100;
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break;
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case IFM_10_T:
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reg = MAC_CON1_GMAC2IO_RMII_CLK_SEL_2_5 |
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MAC_CON1_GMAC2IO_MAC_SPEED_10;
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break;
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default:
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device_printf(sc->base.dev, "unsupported RMII media %u\n", speed);
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return (-1);
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}
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SYSCON_WRITE_4(sc->grf,
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sc->integrated_phy ? RK3328_GRF_MAC_CON2 : RK3328_GRF_MAC_CON1,
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reg |
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((MAC_CON1_GMAC2IO_RMII_CLK_SEL_MASK | MAC_CON1_GMAC2IO_MAC_SPEED_MASK) << 16));
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break;
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}
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return (0);
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}
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static void
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rk3328_set_phy_mode(struct if_dwc_rk_softc *sc)
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{
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switch (sc->base.phy_mode) {
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case PHY_MODE_RGMII:
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SYSCON_WRITE_4(sc->grf, RK3328_GRF_MAC_CON1,
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((MAC_CON1_GMAC2IO_INTF_SEL_MASK | MAC_CON1_GMAC2IO_RMII_MODE_MASK) << 16) |
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MAC_CON1_GMAC2IO_INTF_RGMII);
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break;
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case PHY_MODE_RMII:
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SYSCON_WRITE_4(sc->grf, sc->integrated_phy ? RK3328_GRF_MAC_CON2 : RK3328_GRF_MAC_CON1,
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((MAC_CON1_GMAC2IO_INTF_SEL_MASK | MAC_CON1_GMAC2IO_RMII_MODE_MASK) << 16) |
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MAC_CON1_GMAC2IO_INTF_RMII | MAC_CON1_GMAC2IO_RMII_MODE);
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break;
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}
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}
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static void
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rk3328_phy_powerup(struct if_dwc_rk_softc *sc)
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{
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SYSCON_WRITE_4(sc->grf, RK3328_GRF_MACPHY_CON1,
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(MACPHY_CON1_RMII_MODE_MASK << 16) |
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MACPHY_CON1_RMII_MODE);
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}
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static void
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rk3399_set_delays(struct if_dwc_rk_softc *sc)
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{
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uint32_t reg, tx, rx;
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if (sc->base.phy_mode != PHY_MODE_RGMII)
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return;
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reg = SYSCON_READ_4(sc->grf, RK3399_GRF_SOC_CON6);
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tx = ((reg >> SOC_CON6_TX_DL_CFG_SHIFT) & SOC_CON6_TX_DL_CFG_MASK);
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rx = ((reg >> SOC_CON6_RX_DL_CFG_SHIFT) & SOC_CON6_RX_DL_CFG_MASK);
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if (bootverbose) {
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device_printf(sc->base.dev, "current delays settings: tx=%u(%s) rx=%u(%s)\n",
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tx, ((reg & SOC_CON6_GMAC_TXCLK_DLY_ENA) ? "enabled" : "disabled"),
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rx, ((reg & SOC_CON6_GMAC_RXCLK_DLY_ENA) ? "enabled" : "disabled"));
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device_printf(sc->base.dev, "setting new RK3399 RX/TX delays: %d/%d\n",
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sc->rx_delay, sc->tx_delay);
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}
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reg = 0xFFFF << 16;
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reg |= ((sc->tx_delay & SOC_CON6_TX_DL_CFG_MASK) <<
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SOC_CON6_TX_DL_CFG_SHIFT);
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reg |= ((sc->rx_delay & SOC_CON6_RX_DL_CFG_MASK) <<
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SOC_CON6_RX_DL_CFG_SHIFT);
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reg |= SOC_CON6_GMAC_TXCLK_DLY_ENA | SOC_CON6_GMAC_RXCLK_DLY_ENA;
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SYSCON_WRITE_4(sc->grf, RK3399_GRF_SOC_CON6, reg);
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}
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static int
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rk3399_set_speed(struct if_dwc_rk_softc *sc, int speed)
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{
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uint32_t reg;
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switch (speed) {
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case IFM_1000_T:
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case IFM_1000_SX:
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reg = SOC_CON5_GMAC_CLK_SEL_125;
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break;
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case IFM_100_TX:
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reg = SOC_CON5_GMAC_CLK_SEL_25;
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break;
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case IFM_10_T:
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reg = SOC_CON5_GMAC_CLK_SEL_2_5;
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break;
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default:
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device_printf(sc->base.dev, "unsupported media %u\n", speed);
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return (-1);
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}
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SYSCON_WRITE_4(sc->grf, RK3399_GRF_SOC_CON5,
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((SOC_CON5_GMAC_CLK_SEL_MASK << 16) | reg));
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return (0);
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}
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static int
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if_dwc_rk_sysctl_delays(SYSCTL_HANDLER_ARGS)
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{
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struct if_dwc_rk_softc *sc;
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int rv;
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uint32_t rxtx;
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sc = arg1;
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rxtx = ((sc->rx_delay << 8) | sc->tx_delay);
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rv = sysctl_handle_int(oidp, &rxtx, 0, req);
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if (rv != 0 || req->newptr == NULL)
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return (rv);
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sc->tx_delay = rxtx & 0xff;
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sc->rx_delay = (rxtx >> 8) & 0xff;
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if (sc->ops->set_delays)
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sc->ops->set_delays(sc);
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return (0);
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}
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static int
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if_dwc_rk_init_sysctl(struct if_dwc_rk_softc *sc)
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{
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struct sysctl_oid *child;
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struct sysctl_ctx_list *ctx_list;
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ctx_list = device_get_sysctl_ctx(sc->base.dev);
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child = device_get_sysctl_tree(sc->base.dev);
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SYSCTL_ADD_PROC(ctx_list,
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SYSCTL_CHILDREN(child), OID_AUTO, "delays",
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CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, sc, 0,
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if_dwc_rk_sysctl_delays, "", "RGMII RX/TX delays: ((rx << 8) | tx)");
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return (0);
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}
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static int
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if_dwc_rk_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Rockchip Gigabit Ethernet Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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if_dwc_rk_init_clocks(device_t dev)
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{
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struct if_dwc_rk_softc *sc;
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int error;
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sc = device_get_softc(dev);
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error = clk_set_assigned(dev, ofw_bus_get_node(dev));
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if (error != 0) {
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device_printf(dev, "clk_set_assigned failed\n");
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return (error);
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}
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/* Enable clocks */
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error = clk_get_by_ofw_name(dev, 0, "stmmaceth", &sc->clk_stmmaceth);
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if (error != 0) {
|
|
device_printf(dev, "could not find clock stmmaceth\n");
|
|
return (error);
|
|
}
|
|
|
|
if (clk_get_by_ofw_name(dev, 0, "mac_clk_rx", &sc->mac_clk_rx) != 0) {
|
|
device_printf(sc->base.dev, "could not get mac_clk_rx clock\n");
|
|
sc->mac_clk_rx = NULL;
|
|
}
|
|
|
|
if (clk_get_by_ofw_name(dev, 0, "mac_clk_tx", &sc->mac_clk_tx) != 0) {
|
|
device_printf(sc->base.dev, "could not get mac_clk_tx clock\n");
|
|
sc->mac_clk_tx = NULL;
|
|
}
|
|
|
|
if (clk_get_by_ofw_name(dev, 0, "aclk_mac", &sc->aclk_mac) != 0) {
|
|
device_printf(sc->base.dev, "could not get aclk_mac clock\n");
|
|
sc->aclk_mac = NULL;
|
|
}
|
|
|
|
if (clk_get_by_ofw_name(dev, 0, "pclk_mac", &sc->pclk_mac) != 0) {
|
|
device_printf(sc->base.dev, "could not get pclk_mac clock\n");
|
|
sc->pclk_mac = NULL;
|
|
}
|
|
|
|
if (sc->base.phy_mode == PHY_MODE_RGMII) {
|
|
if (clk_get_by_ofw_name(dev, 0, "clk_mac_ref", &sc->clk_mac_ref) != 0) {
|
|
device_printf(sc->base.dev, "could not get clk_mac_ref clock\n");
|
|
sc->clk_mac_ref = NULL;
|
|
}
|
|
|
|
if (!sc->clock_in) {
|
|
if (clk_get_by_ofw_name(dev, 0, "clk_mac_refout", &sc->clk_mac_refout) != 0) {
|
|
device_printf(sc->base.dev, "could not get clk_mac_refout clock\n");
|
|
sc->clk_mac_refout = NULL;
|
|
}
|
|
|
|
clk_set_freq(sc->clk_stmmaceth, 50000000, 0);
|
|
}
|
|
}
|
|
|
|
if ((sc->phy_node != 0) && sc->integrated_phy) {
|
|
if (clk_get_by_ofw_index(dev, sc->phy_node, 0, &sc->clk_phy) != 0) {
|
|
device_printf(sc->base.dev, "could not get PHY clock\n");
|
|
sc->clk_phy = NULL;
|
|
}
|
|
|
|
if (sc->clk_phy) {
|
|
clk_set_freq(sc->clk_phy, 50000000, 0);
|
|
}
|
|
}
|
|
|
|
if (sc->base.phy_mode == PHY_MODE_RMII) {
|
|
if (sc->mac_clk_rx)
|
|
clk_enable(sc->mac_clk_rx);
|
|
if (sc->clk_mac_ref)
|
|
clk_enable(sc->clk_mac_ref);
|
|
if (sc->clk_mac_refout)
|
|
clk_enable(sc->clk_mac_refout);
|
|
}
|
|
if (sc->clk_phy)
|
|
clk_enable(sc->clk_phy);
|
|
if (sc->aclk_mac)
|
|
clk_enable(sc->aclk_mac);
|
|
if (sc->pclk_mac)
|
|
clk_enable(sc->pclk_mac);
|
|
if (sc->mac_clk_tx)
|
|
clk_enable(sc->mac_clk_tx);
|
|
|
|
DELAY(50);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
if_dwc_rk_init(device_t dev)
|
|
{
|
|
struct if_dwc_rk_softc *sc;
|
|
phandle_t node;
|
|
uint32_t rx, tx;
|
|
int err;
|
|
pcell_t phy_handle;
|
|
char *clock_in_out;
|
|
hwreset_t phy_reset;
|
|
regulator_t phy_supply;
|
|
|
|
sc = device_get_softc(dev);
|
|
node = ofw_bus_get_node(dev);
|
|
sc->ops = (struct if_dwc_rk_ops *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
|
|
if (OF_hasprop(node, "rockchip,grf") &&
|
|
syscon_get_by_ofw_property(dev, node,
|
|
"rockchip,grf", &sc->grf) != 0) {
|
|
device_printf(dev, "cannot get grf driver handle\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
if (OF_getencprop(node, "tx_delay", &tx, sizeof(tx)) <= 0)
|
|
tx = 0x30;
|
|
if (OF_getencprop(node, "rx_delay", &rx, sizeof(rx)) <= 0)
|
|
rx = 0x10;
|
|
sc->tx_delay = tx;
|
|
sc->rx_delay = rx;
|
|
|
|
sc->clock_in = true;
|
|
if (OF_getprop_alloc(node, "clock_in_out", (void **)&clock_in_out)) {
|
|
if (strcmp(clock_in_out, "input") == 0)
|
|
sc->clock_in = true;
|
|
else
|
|
sc->clock_in = false;
|
|
OF_prop_free(clock_in_out);
|
|
}
|
|
|
|
if (OF_getencprop(node, "phy-handle", (void *)&phy_handle,
|
|
sizeof(phy_handle)) > 0)
|
|
sc->phy_node = OF_node_from_xref(phy_handle);
|
|
|
|
if (sc->phy_node)
|
|
sc->integrated_phy = OF_hasprop(sc->phy_node, "phy-is-integrated");
|
|
|
|
if (sc->integrated_phy)
|
|
device_printf(sc->base.dev, "PHY is integrated\n");
|
|
|
|
if_dwc_rk_init_clocks(dev);
|
|
|
|
if (sc->ops->set_phy_mode)
|
|
sc->ops->set_phy_mode(sc);
|
|
|
|
if (sc->ops->set_delays)
|
|
sc->ops->set_delays(sc);
|
|
|
|
/*
|
|
* this also sets delays if tunable is defined
|
|
*/
|
|
err = if_dwc_rk_init_sysctl(sc);
|
|
if (err != 0)
|
|
return (err);
|
|
|
|
if (regulator_get_by_ofw_property(sc->base.dev, 0,
|
|
"phy-supply", &phy_supply) == 0) {
|
|
if (regulator_enable(phy_supply)) {
|
|
device_printf(sc->base.dev,
|
|
"cannot enable 'phy' regulator\n");
|
|
}
|
|
}
|
|
else
|
|
device_printf(sc->base.dev, "no phy-supply property\n");
|
|
|
|
/* Power up */
|
|
if (sc->integrated_phy) {
|
|
if (sc->ops->phy_powerup)
|
|
sc->ops->phy_powerup(sc);
|
|
|
|
SYSCON_WRITE_4(sc->grf, RK3328_GRF_MACPHY_CON0,
|
|
(MACPHY_CON0_CLK_50M_MASK << 16) |
|
|
MACPHY_CON0_CLK_50M);
|
|
SYSCON_WRITE_4(sc->grf, RK3328_GRF_MACPHY_CON0,
|
|
(MACPHY_CON0_RMII_MODE_MASK << 16) |
|
|
MACPHY_CON0_RMII_MODE);
|
|
SYSCON_WRITE_4(sc->grf, RK3328_GRF_MACPHY_CON2, 0xffff1234);
|
|
SYSCON_WRITE_4(sc->grf, RK3328_GRF_MACPHY_CON3, 0x003f0035);
|
|
|
|
if (hwreset_get_by_ofw_idx(dev, sc->phy_node, 0, &phy_reset) == 0) {
|
|
hwreset_assert(phy_reset);
|
|
DELAY(20);
|
|
hwreset_deassert(phy_reset);
|
|
DELAY(20);
|
|
}
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
if_dwc_rk_mac_type(device_t dev)
|
|
{
|
|
|
|
return (DWC_GMAC_NORMAL_DESC);
|
|
}
|
|
|
|
static int
|
|
if_dwc_rk_mii_clk(device_t dev)
|
|
{
|
|
|
|
/* Should be calculated from the clock */
|
|
return (GMAC_MII_CLK_150_250M_DIV102);
|
|
}
|
|
|
|
static int
|
|
if_dwc_rk_set_speed(device_t dev, int speed)
|
|
{
|
|
struct if_dwc_rk_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (sc->ops->set_speed)
|
|
return sc->ops->set_speed(sc, speed);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t if_dwc_rk_methods[] = {
|
|
DEVMETHOD(device_probe, if_dwc_rk_probe),
|
|
|
|
DEVMETHOD(if_dwc_init, if_dwc_rk_init),
|
|
DEVMETHOD(if_dwc_mac_type, if_dwc_rk_mac_type),
|
|
DEVMETHOD(if_dwc_mii_clk, if_dwc_rk_mii_clk),
|
|
DEVMETHOD(if_dwc_set_speed, if_dwc_rk_set_speed),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static devclass_t dwc_rk_devclass;
|
|
|
|
extern driver_t dwc_driver;
|
|
|
|
DEFINE_CLASS_1(dwc, dwc_rk_driver, if_dwc_rk_methods,
|
|
sizeof(struct if_dwc_rk_softc), dwc_driver);
|
|
DRIVER_MODULE(dwc_rk, simplebus, dwc_rk_driver, dwc_rk_devclass, 0, 0);
|
|
MODULE_DEPEND(dwc_rk, dwc, 1, 1, 1);
|