2001-05-11 19:56:39 +00:00
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/*
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* Copyright (c) 2001 Wind River Systems
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* Copyright (c) 1997, 1998, 1999, 2000, 2001
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* Bill Paul <wpaul@bsdi.com>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2003-08-24 17:55:58 +00:00
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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2001-05-11 19:56:39 +00:00
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/*
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* National Semiconductor DP83820/DP83821 gigabit ethernet driver
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* for FreeBSD. Datasheets are available from:
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*
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* http://www.national.com/ds/DP/DP83820.pdf
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* http://www.national.com/ds/DP/DP83821.pdf
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*
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* These chips are used on several low cost gigabit ethernet NICs
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* sold by D-Link, Addtron, SMC and Asante. Both parts are
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* virtually the same, except the 83820 is a 64-bit/32-bit part,
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* while the 83821 is 32-bit only.
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*
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* Many cards also use National gigE transceivers, such as the
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* DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
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* contains a full register description that applies to all of these
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* components:
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*
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* http://www.national.com/ds/DP/DP83861.pdf
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*
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* Written by Bill Paul <wpaul@bsdi.com>
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* BSDi Open Source Solutions
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*/
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/*
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* The NatSemi DP83820 and 83821 controllers are enhanced versions
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* of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
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* and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
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* ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
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* hardware checksum offload (IPv4 only), VLAN tagging and filtering,
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* priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
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* matching buffers, one perfect address filter buffer and interrupt
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* moderation. The 83820 supports both 64-bit and 32-bit addressing
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* and data transfers: the 64-bit support can be toggled on or off
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* via software. This affects the size of certain fields in the DMA
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* descriptors.
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*
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2001-06-16 03:38:44 +00:00
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* There are two bugs/misfeatures in the 83820/83821 that I have
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* discovered so far:
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*
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* - Receive buffers must be aligned on 64-bit boundaries, which means
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* you must resort to copying data in order to fix up the payload
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* alignment.
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*
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* - In order to transmit jumbo frames larger than 8170 bytes, you have
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* to turn off transmit checksum offloading, because the chip can't
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* compute the checksum on an outgoing frame unless it fits entirely
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* within the TX FIFO, which is only 8192 bytes in size. If you have
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* TX checksum offload enabled and you transmit attempt to transmit a
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* frame larger than 8170 bytes, the transmitter will wedge.
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*
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* To work around the latter problem, TX checksum offload is disabled
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* if the user selects an MTU larger than 8152 (8170 - 18).
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2001-05-11 19:56:39 +00:00
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/sockio.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/ethernet.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include <net/if_vlan_var.h>
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#include <net/bpf.h>
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#include <vm/vm.h> /* for vtophys */
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#include <vm/pmap.h> /* for vtophys */
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#include <machine/clock.h> /* for DELAY */
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#include <machine/bus_pio.h>
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#include <machine/bus_memio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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2003-08-22 06:42:59 +00:00
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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2001-05-11 19:56:39 +00:00
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#define NGE_USEIOSPACE
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2001-05-12 19:51:40 +00:00
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#include <dev/nge/if_ngereg.h>
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2001-05-11 19:56:39 +00:00
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2003-04-15 06:37:30 +00:00
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MODULE_DEPEND(nge, pci, 1, 1, 1);
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MODULE_DEPEND(nge, ether, 1, 1, 1);
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2001-05-11 19:56:39 +00:00
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MODULE_DEPEND(nge, miibus, 1, 1, 1);
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/* "controller miibus0" required. See GENERIC if you get errors here. */
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#include "miibus_if.h"
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#define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
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/*
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* Various supported device vendors/types and their names.
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*/
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static struct nge_type nge_devs[] = {
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{ NGE_VENDORID, NGE_DEVICEID,
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"National Semiconductor Gigabit Ethernet" },
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{ 0, 0, NULL }
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};
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2002-07-06 15:59:57 +00:00
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static int nge_probe(device_t);
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static int nge_attach(device_t);
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static int nge_detach(device_t);
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static int nge_alloc_jumbo_mem(struct nge_softc *);
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static void nge_free_jumbo_mem(struct nge_softc *);
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static void *nge_jalloc(struct nge_softc *);
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static void nge_jfree(void *, void *);
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static int nge_newbuf(struct nge_softc *, struct nge_desc *, struct mbuf *);
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static int nge_encap(struct nge_softc *, struct mbuf *, u_int32_t *);
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static void nge_rxeof(struct nge_softc *);
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static void nge_txeof(struct nge_softc *);
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static void nge_intr(void *);
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static void nge_tick(void *);
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static void nge_start(struct ifnet *);
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static int nge_ioctl(struct ifnet *, u_long, caddr_t);
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static void nge_init(void *);
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static void nge_stop(struct nge_softc *);
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static void nge_watchdog(struct ifnet *);
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static void nge_shutdown(device_t);
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static int nge_ifmedia_upd(struct ifnet *);
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static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
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static void nge_delay(struct nge_softc *);
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static void nge_eeprom_idle(struct nge_softc *);
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static void nge_eeprom_putbyte(struct nge_softc *, int);
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static void nge_eeprom_getword(struct nge_softc *, int, u_int16_t *);
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static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int, int);
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static void nge_mii_sync(struct nge_softc *);
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static void nge_mii_send(struct nge_softc *, u_int32_t, int);
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static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
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static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
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static int nge_miibus_readreg(device_t, int, int);
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static int nge_miibus_writereg(device_t, int, int, int);
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static void nge_miibus_statchg(device_t);
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static void nge_setmulti(struct nge_softc *);
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2003-12-08 07:54:15 +00:00
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static uint32_t nge_mchash(const uint8_t *);
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2002-07-06 15:59:57 +00:00
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static void nge_reset(struct nge_softc *);
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static int nge_list_rx_init(struct nge_softc *);
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static int nge_list_tx_init(struct nge_softc *);
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2001-05-11 19:56:39 +00:00
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#ifdef NGE_USEIOSPACE
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#define NGE_RES SYS_RES_IOPORT
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#define NGE_RID NGE_PCI_LOIO
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#else
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#define NGE_RES SYS_RES_MEMORY
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#define NGE_RID NGE_PCI_LOMEM
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#endif
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static device_method_t nge_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, nge_probe),
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DEVMETHOD(device_attach, nge_attach),
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DEVMETHOD(device_detach, nge_detach),
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DEVMETHOD(device_shutdown, nge_shutdown),
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/* bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_driver_added, bus_generic_driver_added),
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/* MII interface */
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DEVMETHOD(miibus_readreg, nge_miibus_readreg),
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DEVMETHOD(miibus_writereg, nge_miibus_writereg),
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DEVMETHOD(miibus_statchg, nge_miibus_statchg),
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{ 0, 0 }
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};
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static driver_t nge_driver = {
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"nge",
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nge_methods,
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sizeof(struct nge_softc)
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};
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static devclass_t nge_devclass;
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2003-04-15 06:37:30 +00:00
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DRIVER_MODULE(nge, pci, nge_driver, nge_devclass, 0, 0);
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2001-05-11 19:56:39 +00:00
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DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
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#define NGE_SETBIT(sc, reg, x) \
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CSR_WRITE_4(sc, reg, \
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CSR_READ_4(sc, reg) | (x))
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#define NGE_CLRBIT(sc, reg, x) \
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CSR_WRITE_4(sc, reg, \
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CSR_READ_4(sc, reg) & ~(x))
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#define SIO_SET(x) \
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2002-11-09 12:55:07 +00:00
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CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
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2001-05-11 19:56:39 +00:00
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#define SIO_CLR(x) \
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2002-11-09 12:55:07 +00:00
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CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
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2001-05-11 19:56:39 +00:00
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2002-07-06 15:59:57 +00:00
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static void
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nge_delay(sc)
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2001-05-11 19:56:39 +00:00
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struct nge_softc *sc;
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{
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int idx;
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for (idx = (300 / 33) + 1; idx > 0; idx--)
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CSR_READ_4(sc, NGE_CSR);
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return;
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}
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2002-07-06 15:59:57 +00:00
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static void
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nge_eeprom_idle(sc)
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2001-05-11 19:56:39 +00:00
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struct nge_softc *sc;
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{
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register int i;
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SIO_SET(NGE_MEAR_EE_CSEL);
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nge_delay(sc);
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SIO_SET(NGE_MEAR_EE_CLK);
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nge_delay(sc);
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for (i = 0; i < 25; i++) {
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SIO_CLR(NGE_MEAR_EE_CLK);
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nge_delay(sc);
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SIO_SET(NGE_MEAR_EE_CLK);
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nge_delay(sc);
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}
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SIO_CLR(NGE_MEAR_EE_CLK);
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nge_delay(sc);
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SIO_CLR(NGE_MEAR_EE_CSEL);
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nge_delay(sc);
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CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
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return;
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}
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/*
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* Send a read command and address to the EEPROM, check for ACK.
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*/
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2002-07-06 15:59:57 +00:00
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static void
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nge_eeprom_putbyte(sc, addr)
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2001-05-11 19:56:39 +00:00
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struct nge_softc *sc;
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int addr;
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{
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register int d, i;
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d = addr | NGE_EECMD_READ;
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/*
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* Feed in each bit and stobe the clock.
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*/
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for (i = 0x400; i; i >>= 1) {
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if (d & i) {
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SIO_SET(NGE_MEAR_EE_DIN);
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} else {
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SIO_CLR(NGE_MEAR_EE_DIN);
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}
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nge_delay(sc);
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SIO_SET(NGE_MEAR_EE_CLK);
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nge_delay(sc);
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SIO_CLR(NGE_MEAR_EE_CLK);
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nge_delay(sc);
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}
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return;
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}
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/*
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* Read a word of data stored in the EEPROM at address 'addr.'
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*/
|
2002-07-06 15:59:57 +00:00
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static void
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nge_eeprom_getword(sc, addr, dest)
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2001-05-11 19:56:39 +00:00
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struct nge_softc *sc;
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int addr;
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u_int16_t *dest;
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{
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register int i;
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u_int16_t word = 0;
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/* Force EEPROM to idle state. */
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nge_eeprom_idle(sc);
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|
|
/* Enter EEPROM access mode. */
|
|
|
|
nge_delay(sc);
|
|
|
|
SIO_CLR(NGE_MEAR_EE_CLK);
|
|
|
|
nge_delay(sc);
|
|
|
|
SIO_SET(NGE_MEAR_EE_CSEL);
|
|
|
|
nge_delay(sc);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Send address of word we want to read.
|
|
|
|
*/
|
|
|
|
nge_eeprom_putbyte(sc, addr);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Start reading bits from EEPROM.
|
|
|
|
*/
|
|
|
|
for (i = 0x8000; i; i >>= 1) {
|
|
|
|
SIO_SET(NGE_MEAR_EE_CLK);
|
|
|
|
nge_delay(sc);
|
|
|
|
if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
|
|
|
|
word |= i;
|
|
|
|
nge_delay(sc);
|
|
|
|
SIO_CLR(NGE_MEAR_EE_CLK);
|
|
|
|
nge_delay(sc);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Turn off EEPROM access mode. */
|
|
|
|
nge_eeprom_idle(sc);
|
|
|
|
|
|
|
|
*dest = word;
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Read a sequence of words from the EEPROM.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_read_eeprom(sc, dest, off, cnt, swap)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
caddr_t dest;
|
|
|
|
int off;
|
|
|
|
int cnt;
|
|
|
|
int swap;
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
u_int16_t word = 0, *ptr;
|
|
|
|
|
|
|
|
for (i = 0; i < cnt; i++) {
|
|
|
|
nge_eeprom_getword(sc, off + i, &word);
|
|
|
|
ptr = (u_int16_t *)(dest + (i * 2));
|
|
|
|
if (swap)
|
|
|
|
*ptr = ntohs(word);
|
|
|
|
else
|
|
|
|
*ptr = word;
|
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Sync the PHYs by setting data bit and strobing the clock 32 times.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_mii_sync(sc)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
{
|
|
|
|
register int i;
|
|
|
|
|
|
|
|
SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA);
|
|
|
|
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
SIO_SET(NGE_MEAR_MII_CLK);
|
|
|
|
DELAY(1);
|
|
|
|
SIO_CLR(NGE_MEAR_MII_CLK);
|
|
|
|
DELAY(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clock a series of bits through the MII.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_mii_send(sc, bits, cnt)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
u_int32_t bits;
|
|
|
|
int cnt;
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
SIO_CLR(NGE_MEAR_MII_CLK);
|
|
|
|
|
|
|
|
for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
|
|
|
|
if (bits & i) {
|
|
|
|
SIO_SET(NGE_MEAR_MII_DATA);
|
|
|
|
} else {
|
|
|
|
SIO_CLR(NGE_MEAR_MII_DATA);
|
|
|
|
}
|
|
|
|
DELAY(1);
|
|
|
|
SIO_CLR(NGE_MEAR_MII_CLK);
|
|
|
|
DELAY(1);
|
|
|
|
SIO_SET(NGE_MEAR_MII_CLK);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Read an PHY register through the MII.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static int
|
|
|
|
nge_mii_readreg(sc, frame)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
struct nge_mii_frame *frame;
|
|
|
|
|
|
|
|
{
|
|
|
|
int i, ack, s;
|
|
|
|
|
|
|
|
s = splimp();
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set up frame for RX.
|
|
|
|
*/
|
|
|
|
frame->mii_stdelim = NGE_MII_STARTDELIM;
|
|
|
|
frame->mii_opcode = NGE_MII_READOP;
|
|
|
|
frame->mii_turnaround = 0;
|
|
|
|
frame->mii_data = 0;
|
|
|
|
|
|
|
|
CSR_WRITE_4(sc, NGE_MEAR, 0);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Turn on data xmit.
|
|
|
|
*/
|
|
|
|
SIO_SET(NGE_MEAR_MII_DIR);
|
|
|
|
|
|
|
|
nge_mii_sync(sc);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Send command/address info.
|
|
|
|
*/
|
|
|
|
nge_mii_send(sc, frame->mii_stdelim, 2);
|
|
|
|
nge_mii_send(sc, frame->mii_opcode, 2);
|
|
|
|
nge_mii_send(sc, frame->mii_phyaddr, 5);
|
|
|
|
nge_mii_send(sc, frame->mii_regaddr, 5);
|
|
|
|
|
|
|
|
/* Idle bit */
|
|
|
|
SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA));
|
|
|
|
DELAY(1);
|
|
|
|
SIO_SET(NGE_MEAR_MII_CLK);
|
|
|
|
DELAY(1);
|
|
|
|
|
|
|
|
/* Turn off xmit. */
|
|
|
|
SIO_CLR(NGE_MEAR_MII_DIR);
|
|
|
|
/* Check for ack */
|
|
|
|
SIO_CLR(NGE_MEAR_MII_CLK);
|
|
|
|
DELAY(1);
|
2003-01-10 08:09:58 +00:00
|
|
|
ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
|
2001-05-11 19:56:39 +00:00
|
|
|
SIO_SET(NGE_MEAR_MII_CLK);
|
|
|
|
DELAY(1);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Now try reading data bits. If the ack failed, we still
|
|
|
|
* need to clock through 16 cycles to keep the PHY(s) in sync.
|
|
|
|
*/
|
|
|
|
if (ack) {
|
|
|
|
for(i = 0; i < 16; i++) {
|
|
|
|
SIO_CLR(NGE_MEAR_MII_CLK);
|
|
|
|
DELAY(1);
|
|
|
|
SIO_SET(NGE_MEAR_MII_CLK);
|
|
|
|
DELAY(1);
|
|
|
|
}
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0x8000; i; i >>= 1) {
|
|
|
|
SIO_CLR(NGE_MEAR_MII_CLK);
|
|
|
|
DELAY(1);
|
|
|
|
if (!ack) {
|
|
|
|
if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
|
|
|
|
frame->mii_data |= i;
|
|
|
|
DELAY(1);
|
|
|
|
}
|
|
|
|
SIO_SET(NGE_MEAR_MII_CLK);
|
|
|
|
DELAY(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
fail:
|
|
|
|
|
|
|
|
SIO_CLR(NGE_MEAR_MII_CLK);
|
|
|
|
DELAY(1);
|
|
|
|
SIO_SET(NGE_MEAR_MII_CLK);
|
|
|
|
DELAY(1);
|
|
|
|
|
|
|
|
splx(s);
|
|
|
|
|
|
|
|
if (ack)
|
|
|
|
return(1);
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Write to a PHY register through the MII.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static int
|
|
|
|
nge_mii_writereg(sc, frame)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
struct nge_mii_frame *frame;
|
|
|
|
|
|
|
|
{
|
|
|
|
int s;
|
|
|
|
|
|
|
|
s = splimp();
|
|
|
|
/*
|
|
|
|
* Set up frame for TX.
|
|
|
|
*/
|
|
|
|
|
|
|
|
frame->mii_stdelim = NGE_MII_STARTDELIM;
|
|
|
|
frame->mii_opcode = NGE_MII_WRITEOP;
|
|
|
|
frame->mii_turnaround = NGE_MII_TURNAROUND;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Turn on data output.
|
|
|
|
*/
|
|
|
|
SIO_SET(NGE_MEAR_MII_DIR);
|
|
|
|
|
|
|
|
nge_mii_sync(sc);
|
|
|
|
|
|
|
|
nge_mii_send(sc, frame->mii_stdelim, 2);
|
|
|
|
nge_mii_send(sc, frame->mii_opcode, 2);
|
|
|
|
nge_mii_send(sc, frame->mii_phyaddr, 5);
|
|
|
|
nge_mii_send(sc, frame->mii_regaddr, 5);
|
|
|
|
nge_mii_send(sc, frame->mii_turnaround, 2);
|
|
|
|
nge_mii_send(sc, frame->mii_data, 16);
|
|
|
|
|
|
|
|
/* Idle bit. */
|
|
|
|
SIO_SET(NGE_MEAR_MII_CLK);
|
|
|
|
DELAY(1);
|
|
|
|
SIO_CLR(NGE_MEAR_MII_CLK);
|
|
|
|
DELAY(1);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Turn off xmit.
|
|
|
|
*/
|
|
|
|
SIO_CLR(NGE_MEAR_MII_DIR);
|
|
|
|
|
|
|
|
splx(s);
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
2002-07-06 15:59:57 +00:00
|
|
|
static int
|
|
|
|
nge_miibus_readreg(dev, phy, reg)
|
2001-05-11 19:56:39 +00:00
|
|
|
device_t dev;
|
|
|
|
int phy, reg;
|
|
|
|
{
|
|
|
|
struct nge_softc *sc;
|
|
|
|
struct nge_mii_frame frame;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
bzero((char *)&frame, sizeof(frame));
|
|
|
|
|
|
|
|
frame.mii_phyaddr = phy;
|
|
|
|
frame.mii_regaddr = reg;
|
|
|
|
nge_mii_readreg(sc, &frame);
|
|
|
|
|
|
|
|
return(frame.mii_data);
|
|
|
|
}
|
|
|
|
|
2002-07-06 15:59:57 +00:00
|
|
|
static int
|
|
|
|
nge_miibus_writereg(dev, phy, reg, data)
|
2001-05-11 19:56:39 +00:00
|
|
|
device_t dev;
|
|
|
|
int phy, reg, data;
|
|
|
|
{
|
|
|
|
struct nge_softc *sc;
|
|
|
|
struct nge_mii_frame frame;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
bzero((char *)&frame, sizeof(frame));
|
|
|
|
|
|
|
|
frame.mii_phyaddr = phy;
|
|
|
|
frame.mii_regaddr = reg;
|
|
|
|
frame.mii_data = data;
|
|
|
|
nge_mii_writereg(sc, &frame);
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_miibus_statchg(dev)
|
2001-05-11 19:56:39 +00:00
|
|
|
device_t dev;
|
|
|
|
{
|
2002-08-08 18:33:28 +00:00
|
|
|
int status;
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
struct mii_data *mii;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
2002-08-08 18:33:28 +00:00
|
|
|
if (sc->nge_tbi) {
|
|
|
|
if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
|
|
|
|
== IFM_AUTO) {
|
|
|
|
status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
|
|
|
|
if (status == 0 || status & NGE_TBIANAR_FDX) {
|
|
|
|
NGE_SETBIT(sc, NGE_TX_CFG,
|
|
|
|
(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
|
|
|
|
NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
|
|
|
|
} else {
|
|
|
|
NGE_CLRBIT(sc, NGE_TX_CFG,
|
|
|
|
(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
|
|
|
|
NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
|
|
|
|
}
|
2001-05-11 19:56:39 +00:00
|
|
|
|
2002-08-08 18:33:28 +00:00
|
|
|
} else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
|
|
|
|
!= IFM_FDX) {
|
|
|
|
NGE_CLRBIT(sc, NGE_TX_CFG,
|
|
|
|
(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
|
|
|
|
NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
|
|
|
|
} else {
|
|
|
|
NGE_SETBIT(sc, NGE_TX_CFG,
|
|
|
|
(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
|
|
|
|
NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
|
|
|
|
}
|
2001-05-11 19:56:39 +00:00
|
|
|
} else {
|
2002-08-08 18:33:28 +00:00
|
|
|
mii = device_get_softc(sc->nge_miibus);
|
2001-05-11 19:56:39 +00:00
|
|
|
|
2002-08-08 18:33:28 +00:00
|
|
|
if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
|
|
|
|
NGE_SETBIT(sc, NGE_TX_CFG,
|
|
|
|
(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
|
|
|
|
NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
|
|
|
|
} else {
|
|
|
|
NGE_CLRBIT(sc, NGE_TX_CFG,
|
|
|
|
(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
|
|
|
|
NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
|
|
|
|
}
|
2001-07-08 16:24:01 +00:00
|
|
|
|
2002-08-08 18:33:28 +00:00
|
|
|
/* If we have a 1000Mbps link, set the mode_1000 bit. */
|
|
|
|
if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
|
|
|
|
IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
|
|
|
|
NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
|
|
|
|
} else {
|
|
|
|
NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
|
|
|
|
}
|
|
|
|
}
|
2001-05-11 19:56:39 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2002-07-06 15:59:57 +00:00
|
|
|
static u_int32_t
|
2003-11-13 20:55:53 +00:00
|
|
|
nge_mchash(addr)
|
2003-12-08 07:54:15 +00:00
|
|
|
const uint8_t *addr;
|
2001-05-11 19:56:39 +00:00
|
|
|
{
|
2003-12-08 07:54:15 +00:00
|
|
|
uint32_t crc, carry;
|
|
|
|
int idx, bit;
|
|
|
|
uint8_t data;
|
2001-05-11 19:56:39 +00:00
|
|
|
|
|
|
|
/* Compute CRC for the address value. */
|
|
|
|
crc = 0xFFFFFFFF; /* initial value */
|
|
|
|
|
2003-11-13 20:55:53 +00:00
|
|
|
for (idx = 0; idx < 6; idx++) {
|
|
|
|
for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) {
|
|
|
|
carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01);
|
2001-05-11 19:56:39 +00:00
|
|
|
crc <<= 1;
|
|
|
|
if (carry)
|
|
|
|
crc = (crc ^ 0x04c11db6) | carry;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* return the filter bit position
|
|
|
|
*/
|
|
|
|
|
|
|
|
return((crc >> 21) & 0x00000FFF);
|
|
|
|
}
|
|
|
|
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_setmulti(sc)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
{
|
|
|
|
struct ifnet *ifp;
|
|
|
|
struct ifmultiaddr *ifma;
|
|
|
|
u_int32_t h = 0, i, filtsave;
|
|
|
|
int bit, index;
|
|
|
|
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
|
|
|
|
|
|
|
if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
|
|
|
|
NGE_CLRBIT(sc, NGE_RXFILT_CTL,
|
|
|
|
NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH);
|
|
|
|
NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We have to explicitly enable the multicast hash table
|
|
|
|
* on the NatSemi chip if we want to use it, which we do.
|
|
|
|
* We also have to tell it that we don't want to use the
|
|
|
|
* hash table for matching unicast addresses.
|
|
|
|
*/
|
|
|
|
NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
|
|
|
|
NGE_CLRBIT(sc, NGE_RXFILT_CTL,
|
|
|
|
NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH);
|
|
|
|
|
|
|
|
filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
|
|
|
|
|
|
|
|
/* first, zot all the existing hash bits */
|
|
|
|
for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
|
|
|
|
CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
|
|
|
|
CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* From the 11 bits returned by the crc routine, the top 7
|
|
|
|
* bits represent the 16-bit word in the mcast hash table
|
|
|
|
* that needs to be updated, and the lower 4 bits represent
|
|
|
|
* which bit within that byte needs to be set.
|
|
|
|
*/
|
|
|
|
TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
|
|
|
|
if (ifma->ifma_addr->sa_family != AF_LINK)
|
|
|
|
continue;
|
2003-11-13 20:55:53 +00:00
|
|
|
h = nge_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
|
2001-05-11 19:56:39 +00:00
|
|
|
index = (h >> 4) & 0x7F;
|
|
|
|
bit = h & 0xF;
|
|
|
|
CSR_WRITE_4(sc, NGE_RXFILT_CTL,
|
|
|
|
NGE_FILTADDR_MCAST_LO + (index * 2));
|
|
|
|
NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
|
|
|
|
}
|
|
|
|
|
|
|
|
CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_reset(sc)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
{
|
|
|
|
register int i;
|
|
|
|
|
|
|
|
NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
|
|
|
|
|
|
|
|
for (i = 0; i < NGE_TIMEOUT; i++) {
|
|
|
|
if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i == NGE_TIMEOUT)
|
|
|
|
printf("nge%d: reset never completed\n", sc->nge_unit);
|
|
|
|
|
|
|
|
/* Wait a little while for the chip to get its brains in order. */
|
|
|
|
DELAY(1000);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If this is a NetSemi chip, make sure to clear
|
|
|
|
* PME mode.
|
|
|
|
*/
|
|
|
|
CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
|
|
|
|
CSR_WRITE_4(sc, NGE_CLKRUN, 0);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2002-12-30 21:18:15 +00:00
|
|
|
* Probe for a NatSemi chip. Check the PCI vendor and device
|
2001-05-11 19:56:39 +00:00
|
|
|
* IDs against our list and return a device name if we find a match.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static int
|
|
|
|
nge_probe(dev)
|
2001-05-11 19:56:39 +00:00
|
|
|
device_t dev;
|
|
|
|
{
|
|
|
|
struct nge_type *t;
|
|
|
|
|
|
|
|
t = nge_devs;
|
|
|
|
|
|
|
|
while(t->nge_name != NULL) {
|
|
|
|
if ((pci_get_vendor(dev) == t->nge_vid) &&
|
|
|
|
(pci_get_device(dev) == t->nge_did)) {
|
|
|
|
device_set_desc(dev, t->nge_name);
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
t++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return(ENXIO);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Attach the interface. Allocate softc structures, do ifmedia
|
|
|
|
* setup and ethernet/BPF attach.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static int
|
|
|
|
nge_attach(dev)
|
2001-05-11 19:56:39 +00:00
|
|
|
device_t dev;
|
|
|
|
{
|
|
|
|
int s;
|
|
|
|
u_char eaddr[ETHER_ADDR_LEN];
|
|
|
|
struct nge_softc *sc;
|
|
|
|
struct ifnet *ifp;
|
|
|
|
int unit, error = 0, rid;
|
2002-08-08 18:33:28 +00:00
|
|
|
const char *sep = "";
|
2001-05-11 19:56:39 +00:00
|
|
|
|
|
|
|
s = splimp();
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
unit = device_get_unit(dev);
|
|
|
|
bzero(sc, sizeof(struct nge_softc));
|
|
|
|
|
2002-04-04 21:03:38 +00:00
|
|
|
mtx_init(&sc->nge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
|
|
|
|
MTX_DEF | MTX_RECURSE);
|
2003-07-03 14:00:57 +00:00
|
|
|
#ifndef BURN_BRIDGES
|
2001-05-11 19:56:39 +00:00
|
|
|
/*
|
|
|
|
* Handle power management nonsense.
|
|
|
|
*/
|
|
|
|
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
|
|
|
|
u_int32_t iobase, membase, irq;
|
|
|
|
|
|
|
|
/* Save important PCI config data. */
|
|
|
|
iobase = pci_read_config(dev, NGE_PCI_LOIO, 4);
|
|
|
|
membase = pci_read_config(dev, NGE_PCI_LOMEM, 4);
|
|
|
|
irq = pci_read_config(dev, NGE_PCI_INTLINE, 4);
|
|
|
|
|
|
|
|
/* Reset the power state. */
|
|
|
|
printf("nge%d: chip is in D%d power mode "
|
|
|
|
"-- setting to D0\n", unit,
|
|
|
|
pci_get_powerstate(dev));
|
|
|
|
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
|
|
|
|
|
|
|
|
/* Restore PCI config data. */
|
|
|
|
pci_write_config(dev, NGE_PCI_LOIO, iobase, 4);
|
|
|
|
pci_write_config(dev, NGE_PCI_LOMEM, membase, 4);
|
|
|
|
pci_write_config(dev, NGE_PCI_INTLINE, irq, 4);
|
|
|
|
}
|
2003-07-03 14:00:57 +00:00
|
|
|
#endif
|
2001-05-11 19:56:39 +00:00
|
|
|
/*
|
|
|
|
* Map control/status registers.
|
|
|
|
*/
|
|
|
|
pci_enable_busmaster(dev);
|
|
|
|
|
|
|
|
rid = NGE_RID;
|
2004-03-17 17:50:55 +00:00
|
|
|
sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE);
|
2001-05-11 19:56:39 +00:00
|
|
|
|
|
|
|
if (sc->nge_res == NULL) {
|
|
|
|
printf("nge%d: couldn't map ports/memory\n", unit);
|
|
|
|
error = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
sc->nge_btag = rman_get_bustag(sc->nge_res);
|
|
|
|
sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
|
|
|
|
|
|
|
|
/* Allocate interrupt */
|
|
|
|
rid = 0;
|
2004-03-17 17:50:55 +00:00
|
|
|
sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
|
2001-05-11 19:56:39 +00:00
|
|
|
RF_SHAREABLE | RF_ACTIVE);
|
|
|
|
|
|
|
|
if (sc->nge_irq == NULL) {
|
|
|
|
printf("nge%d: couldn't map interrupt\n", unit);
|
|
|
|
bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
|
|
|
|
error = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET,
|
|
|
|
nge_intr, sc, &sc->nge_intrhand);
|
|
|
|
|
|
|
|
if (error) {
|
|
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
|
|
|
|
bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
|
|
|
|
printf("nge%d: couldn't set up irq\n", unit);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Reset the adapter. */
|
|
|
|
nge_reset(sc);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Get station address from the EEPROM.
|
|
|
|
*/
|
|
|
|
nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0);
|
|
|
|
nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0);
|
|
|
|
nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0);
|
|
|
|
|
|
|
|
sc->nge_unit = unit;
|
|
|
|
bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
|
|
|
|
|
|
|
|
sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
|
|
|
|
M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
|
|
|
|
|
|
|
|
if (sc->nge_ldata == NULL) {
|
|
|
|
printf("nge%d: no memory for list buffers!\n", unit);
|
|
|
|
bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
|
|
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
|
|
|
|
bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
|
|
|
|
error = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
bzero(sc->nge_ldata, sizeof(struct nge_list_data));
|
|
|
|
|
|
|
|
/* Try to allocate memory for jumbo buffers. */
|
|
|
|
if (nge_alloc_jumbo_mem(sc)) {
|
|
|
|
printf("nge%d: jumbo buffer allocation failed\n",
|
|
|
|
sc->nge_unit);
|
|
|
|
contigfree(sc->nge_ldata,
|
|
|
|
sizeof(struct nge_list_data), M_DEVBUF);
|
|
|
|
bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
|
|
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
|
|
|
|
bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
|
|
|
|
error = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
|
|
|
ifp->if_softc = sc;
|
2003-10-31 18:32:15 +00:00
|
|
|
if_initname(ifp, device_get_name(dev), device_get_unit(dev));
|
2001-05-11 19:56:39 +00:00
|
|
|
ifp->if_mtu = ETHERMTU;
|
|
|
|
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
|
|
|
|
ifp->if_ioctl = nge_ioctl;
|
|
|
|
ifp->if_output = ether_output;
|
|
|
|
ifp->if_start = nge_start;
|
|
|
|
ifp->if_watchdog = nge_watchdog;
|
|
|
|
ifp->if_init = nge_init;
|
|
|
|
ifp->if_baudrate = 1000000000;
|
|
|
|
ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1;
|
|
|
|
ifp->if_hwassist = NGE_CSUM_FEATURES;
|
2002-11-14 23:54:55 +00:00
|
|
|
ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING;
|
2001-09-18 18:53:41 +00:00
|
|
|
ifp->if_capenable = ifp->if_capabilities;
|
2001-05-11 19:56:39 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Do MII setup.
|
|
|
|
*/
|
|
|
|
if (mii_phy_probe(dev, &sc->nge_miibus,
|
2002-08-08 18:33:28 +00:00
|
|
|
nge_ifmedia_upd, nge_ifmedia_sts)) {
|
|
|
|
if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
|
|
|
|
sc->nge_tbi = 1;
|
|
|
|
device_printf(dev, "Using TBI\n");
|
|
|
|
|
|
|
|
sc->nge_miibus = dev;
|
|
|
|
|
|
|
|
ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
|
|
|
|
nge_ifmedia_sts);
|
|
|
|
#define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
|
|
|
|
#define PRINT(s) printf("%s%s", sep, s); sep = ", "
|
|
|
|
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
|
|
|
|
device_printf(dev, " ");
|
|
|
|
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
|
|
|
|
PRINT("1000baseSX");
|
|
|
|
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
|
|
|
|
PRINT("1000baseSX-FDX");
|
|
|
|
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
|
|
|
|
PRINT("auto");
|
|
|
|
|
|
|
|
printf("\n");
|
|
|
|
#undef ADD
|
|
|
|
#undef PRINT
|
|
|
|
ifmedia_set(&sc->nge_ifmedia,
|
|
|
|
IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
|
|
|
|
|
|
|
|
CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
|
|
|
|
| NGE_GPIO_GP4_OUT
|
|
|
|
| NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
|
|
|
|
| NGE_GPIO_GP3_OUTENB
|
|
|
|
| NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
|
|
|
|
|
|
|
|
} else {
|
|
|
|
printf("nge%d: MII without any PHY!\n", sc->nge_unit);
|
|
|
|
nge_free_jumbo_mem(sc);
|
|
|
|
bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
|
|
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
|
|
|
|
bus_release_resource(dev, NGE_RES, NGE_RID,
|
|
|
|
sc->nge_res);
|
|
|
|
error = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
2001-05-11 19:56:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Call MI attach routine.
|
|
|
|
*/
|
2002-11-14 23:54:55 +00:00
|
|
|
ether_ifattach(ifp, eaddr);
|
2001-05-11 19:56:39 +00:00
|
|
|
callout_handle_init(&sc->nge_stat_ch);
|
|
|
|
|
|
|
|
fail:
|
2002-08-08 18:33:28 +00:00
|
|
|
|
2001-05-11 19:56:39 +00:00
|
|
|
splx(s);
|
|
|
|
mtx_destroy(&sc->nge_mtx);
|
|
|
|
return(error);
|
|
|
|
}
|
|
|
|
|
2002-07-06 15:59:57 +00:00
|
|
|
static int
|
|
|
|
nge_detach(dev)
|
2001-05-11 19:56:39 +00:00
|
|
|
device_t dev;
|
|
|
|
{
|
|
|
|
struct nge_softc *sc;
|
|
|
|
struct ifnet *ifp;
|
|
|
|
int s;
|
|
|
|
|
|
|
|
s = splimp();
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
|
|
|
|
|
|
|
nge_reset(sc);
|
|
|
|
nge_stop(sc);
|
2002-11-14 23:54:55 +00:00
|
|
|
ether_ifdetach(ifp);
|
2001-05-11 19:56:39 +00:00
|
|
|
|
|
|
|
bus_generic_detach(dev);
|
2002-08-08 18:33:28 +00:00
|
|
|
if (!sc->nge_tbi) {
|
|
|
|
device_delete_child(dev, sc->nge_miibus);
|
|
|
|
}
|
2001-05-11 19:56:39 +00:00
|
|
|
bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
|
|
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
|
|
|
|
bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
|
|
|
|
|
|
|
|
contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF);
|
|
|
|
nge_free_jumbo_mem(sc);
|
|
|
|
|
|
|
|
splx(s);
|
|
|
|
mtx_destroy(&sc->nge_mtx);
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize the transmit descriptors.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static int
|
|
|
|
nge_list_tx_init(sc)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
{
|
|
|
|
struct nge_list_data *ld;
|
|
|
|
struct nge_ring_data *cd;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
cd = &sc->nge_cdata;
|
|
|
|
ld = sc->nge_ldata;
|
|
|
|
|
|
|
|
for (i = 0; i < NGE_TX_LIST_CNT; i++) {
|
|
|
|
if (i == (NGE_TX_LIST_CNT - 1)) {
|
|
|
|
ld->nge_tx_list[i].nge_nextdesc =
|
|
|
|
&ld->nge_tx_list[0];
|
|
|
|
ld->nge_tx_list[i].nge_next =
|
|
|
|
vtophys(&ld->nge_tx_list[0]);
|
|
|
|
} else {
|
|
|
|
ld->nge_tx_list[i].nge_nextdesc =
|
|
|
|
&ld->nge_tx_list[i + 1];
|
|
|
|
ld->nge_tx_list[i].nge_next =
|
|
|
|
vtophys(&ld->nge_tx_list[i + 1]);
|
|
|
|
}
|
|
|
|
ld->nge_tx_list[i].nge_mbuf = NULL;
|
|
|
|
ld->nge_tx_list[i].nge_ptr = 0;
|
|
|
|
ld->nge_tx_list[i].nge_ctl = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize the RX descriptors and allocate mbufs for them. Note that
|
|
|
|
* we arrange the descriptors in a closed ring, so that the last descriptor
|
|
|
|
* points back to the first.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static int
|
|
|
|
nge_list_rx_init(sc)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
{
|
|
|
|
struct nge_list_data *ld;
|
|
|
|
struct nge_ring_data *cd;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
ld = sc->nge_ldata;
|
|
|
|
cd = &sc->nge_cdata;
|
|
|
|
|
|
|
|
for (i = 0; i < NGE_RX_LIST_CNT; i++) {
|
|
|
|
if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
|
|
|
|
return(ENOBUFS);
|
|
|
|
if (i == (NGE_RX_LIST_CNT - 1)) {
|
|
|
|
ld->nge_rx_list[i].nge_nextdesc =
|
|
|
|
&ld->nge_rx_list[0];
|
|
|
|
ld->nge_rx_list[i].nge_next =
|
|
|
|
vtophys(&ld->nge_rx_list[0]);
|
|
|
|
} else {
|
|
|
|
ld->nge_rx_list[i].nge_nextdesc =
|
|
|
|
&ld->nge_rx_list[i + 1];
|
|
|
|
ld->nge_rx_list[i].nge_next =
|
|
|
|
vtophys(&ld->nge_rx_list[i + 1]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
cd->nge_rx_prod = 0;
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize an RX descriptor and attach an MBUF cluster.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static int
|
|
|
|
nge_newbuf(sc, c, m)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
struct nge_desc *c;
|
|
|
|
struct mbuf *m;
|
|
|
|
{
|
|
|
|
struct mbuf *m_new = NULL;
|
|
|
|
caddr_t *buf = NULL;
|
|
|
|
|
|
|
|
if (m == NULL) {
|
2003-02-19 05:47:46 +00:00
|
|
|
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
|
2001-05-11 19:56:39 +00:00
|
|
|
if (m_new == NULL) {
|
|
|
|
printf("nge%d: no memory for rx list "
|
|
|
|
"-- packet dropped!\n", sc->nge_unit);
|
|
|
|
return(ENOBUFS);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Allocate the jumbo buffer */
|
|
|
|
buf = nge_jalloc(sc);
|
|
|
|
if (buf == NULL) {
|
|
|
|
#ifdef NGE_VERBOSE
|
|
|
|
printf("nge%d: jumbo allocation failed "
|
|
|
|
"-- packet dropped!\n", sc->nge_unit);
|
|
|
|
#endif
|
|
|
|
m_freem(m_new);
|
|
|
|
return(ENOBUFS);
|
|
|
|
}
|
|
|
|
/* Attach the buffer to the mbuf */
|
|
|
|
m_new->m_data = (void *)buf;
|
2001-06-18 22:04:40 +00:00
|
|
|
m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN;
|
|
|
|
MEXTADD(m_new, buf, NGE_JUMBO_FRAMELEN, nge_jfree,
|
2001-05-15 22:19:50 +00:00
|
|
|
(struct nge_softc *)sc, 0, EXT_NET_DRV);
|
2001-05-11 19:56:39 +00:00
|
|
|
} else {
|
|
|
|
m_new = m;
|
2001-06-18 22:04:40 +00:00
|
|
|
m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN;
|
2001-05-11 19:56:39 +00:00
|
|
|
m_new->m_data = m_new->m_ext.ext_buf;
|
|
|
|
}
|
|
|
|
|
|
|
|
m_adj(m_new, sizeof(u_int64_t));
|
|
|
|
|
|
|
|
c->nge_mbuf = m_new;
|
|
|
|
c->nge_ptr = vtophys(mtod(m_new, caddr_t));
|
|
|
|
c->nge_ctl = m_new->m_len;
|
|
|
|
c->nge_extsts = 0;
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
2002-07-06 15:59:57 +00:00
|
|
|
static int
|
|
|
|
nge_alloc_jumbo_mem(sc)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
{
|
|
|
|
caddr_t ptr;
|
|
|
|
register int i;
|
|
|
|
struct nge_jpool_entry *entry;
|
|
|
|
|
|
|
|
/* Grab a big chunk o' storage. */
|
|
|
|
sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF,
|
|
|
|
M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
|
|
|
|
|
|
|
|
if (sc->nge_cdata.nge_jumbo_buf == NULL) {
|
|
|
|
printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit);
|
|
|
|
return(ENOBUFS);
|
|
|
|
}
|
|
|
|
|
|
|
|
SLIST_INIT(&sc->nge_jfree_listhead);
|
|
|
|
SLIST_INIT(&sc->nge_jinuse_listhead);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Now divide it up into 9K pieces and save the addresses
|
|
|
|
* in an array.
|
|
|
|
*/
|
|
|
|
ptr = sc->nge_cdata.nge_jumbo_buf;
|
|
|
|
for (i = 0; i < NGE_JSLOTS; i++) {
|
|
|
|
sc->nge_cdata.nge_jslots[i] = ptr;
|
2001-06-18 22:04:40 +00:00
|
|
|
ptr += NGE_JLEN;
|
2001-05-11 19:56:39 +00:00
|
|
|
entry = malloc(sizeof(struct nge_jpool_entry),
|
|
|
|
M_DEVBUF, M_NOWAIT);
|
|
|
|
if (entry == NULL) {
|
|
|
|
printf("nge%d: no memory for jumbo "
|
|
|
|
"buffer queue!\n", sc->nge_unit);
|
|
|
|
return(ENOBUFS);
|
|
|
|
}
|
|
|
|
entry->slot = i;
|
|
|
|
SLIST_INSERT_HEAD(&sc->nge_jfree_listhead,
|
|
|
|
entry, jpool_entries);
|
|
|
|
}
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_free_jumbo_mem(sc)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
{
|
|
|
|
register int i;
|
|
|
|
struct nge_jpool_entry *entry;
|
|
|
|
|
|
|
|
for (i = 0; i < NGE_JSLOTS; i++) {
|
|
|
|
entry = SLIST_FIRST(&sc->nge_jfree_listhead);
|
|
|
|
SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries);
|
2001-06-18 22:04:40 +00:00
|
|
|
free(entry, M_DEVBUF);
|
2001-05-11 19:56:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Allocate a jumbo buffer.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static void *
|
|
|
|
nge_jalloc(sc)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
{
|
|
|
|
struct nge_jpool_entry *entry;
|
|
|
|
|
|
|
|
entry = SLIST_FIRST(&sc->nge_jfree_listhead);
|
|
|
|
|
|
|
|
if (entry == NULL) {
|
|
|
|
#ifdef NGE_VERBOSE
|
|
|
|
printf("nge%d: no free jumbo buffers\n", sc->nge_unit);
|
|
|
|
#endif
|
|
|
|
return(NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries);
|
|
|
|
SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries);
|
|
|
|
return(sc->nge_cdata.nge_jslots[entry->slot]);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Release a jumbo buffer.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_jfree(buf, args)
|
2002-06-29 01:36:59 +00:00
|
|
|
void *buf;
|
2001-05-11 19:56:39 +00:00
|
|
|
void *args;
|
|
|
|
{
|
|
|
|
struct nge_softc *sc;
|
|
|
|
int i;
|
|
|
|
struct nge_jpool_entry *entry;
|
|
|
|
|
|
|
|
/* Extract the softc struct pointer. */
|
|
|
|
sc = args;
|
|
|
|
|
|
|
|
if (sc == NULL)
|
|
|
|
panic("nge_jfree: can't find softc pointer!");
|
|
|
|
|
|
|
|
/* calculate the slot this buffer belongs to */
|
|
|
|
i = ((vm_offset_t)buf
|
|
|
|
- (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN;
|
|
|
|
|
|
|
|
if ((i < 0) || (i >= NGE_JSLOTS))
|
|
|
|
panic("nge_jfree: asked to free buffer that we don't manage!");
|
|
|
|
|
|
|
|
entry = SLIST_FIRST(&sc->nge_jinuse_listhead);
|
|
|
|
if (entry == NULL)
|
|
|
|
panic("nge_jfree: buffer not in use!");
|
|
|
|
entry->slot = i;
|
|
|
|
SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, jpool_entries);
|
|
|
|
SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jpool_entries);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* A frame has been uploaded: pass the resulting mbuf chain up to
|
|
|
|
* the higher level protocols.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_rxeof(sc)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
{
|
|
|
|
struct mbuf *m;
|
|
|
|
struct ifnet *ifp;
|
|
|
|
struct nge_desc *cur_rx;
|
|
|
|
int i, total_len = 0;
|
|
|
|
u_int32_t rxstat;
|
|
|
|
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
|
|
|
i = sc->nge_cdata.nge_rx_prod;
|
|
|
|
|
|
|
|
while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
|
|
|
|
struct mbuf *m0 = NULL;
|
|
|
|
u_int32_t extsts;
|
|
|
|
|
2002-11-06 15:50:32 +00:00
|
|
|
#ifdef DEVICE_POLLING
|
2004-04-11 16:26:39 +00:00
|
|
|
if (ifp->if_flags & IFF_POLLING) {
|
2002-11-06 15:50:32 +00:00
|
|
|
if (sc->rxcycles <= 0)
|
|
|
|
break;
|
|
|
|
sc->rxcycles--;
|
|
|
|
}
|
|
|
|
#endif /* DEVICE_POLLING */
|
|
|
|
|
2001-05-11 19:56:39 +00:00
|
|
|
cur_rx = &sc->nge_ldata->nge_rx_list[i];
|
|
|
|
rxstat = cur_rx->nge_rxstat;
|
|
|
|
extsts = cur_rx->nge_extsts;
|
|
|
|
m = cur_rx->nge_mbuf;
|
|
|
|
cur_rx->nge_mbuf = NULL;
|
|
|
|
total_len = NGE_RXBYTES(cur_rx);
|
|
|
|
NGE_INC(i, NGE_RX_LIST_CNT);
|
|
|
|
/*
|
|
|
|
* If an error occurs, update stats, clear the
|
|
|
|
* status word and leave the mbuf cluster in place:
|
|
|
|
* it should simply get re-used next time this descriptor
|
|
|
|
* comes up in the ring.
|
|
|
|
*/
|
|
|
|
if (!(rxstat & NGE_CMDSTS_PKT_OK)) {
|
|
|
|
ifp->if_ierrors++;
|
|
|
|
nge_newbuf(sc, cur_rx, m);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Ok. NatSemi really screwed up here. This is the
|
|
|
|
* only gigE chip I know of with alignment constraints
|
|
|
|
* on receive buffers. RX buffers must be 64-bit aligned.
|
|
|
|
*/
|
2001-07-10 23:07:15 +00:00
|
|
|
#ifdef __i386__
|
|
|
|
/*
|
|
|
|
* By popular demand, ignore the alignment problems
|
|
|
|
* on the Intel x86 platform. The performance hit
|
|
|
|
* incurred due to unaligned accesses is much smaller
|
|
|
|
* than the hit produced by forcing buffer copies all
|
|
|
|
* the time, especially with jumbo frames. We still
|
|
|
|
* need to fix up the alignment everywhere else though.
|
|
|
|
*/
|
|
|
|
if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
|
|
|
|
#endif
|
|
|
|
m0 = m_devget(mtod(m, char *), total_len,
|
|
|
|
ETHER_ALIGN, ifp, NULL);
|
|
|
|
nge_newbuf(sc, cur_rx, m);
|
|
|
|
if (m0 == NULL) {
|
|
|
|
printf("nge%d: no receive buffers "
|
|
|
|
"available -- packet dropped!\n",
|
|
|
|
sc->nge_unit);
|
|
|
|
ifp->if_ierrors++;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
m = m0;
|
|
|
|
#ifdef __i386__
|
|
|
|
} else {
|
|
|
|
m->m_pkthdr.rcvif = ifp;
|
|
|
|
m->m_pkthdr.len = m->m_len = total_len;
|
2001-05-11 19:56:39 +00:00
|
|
|
}
|
2001-07-10 23:07:15 +00:00
|
|
|
#endif
|
2001-05-11 19:56:39 +00:00
|
|
|
|
|
|
|
ifp->if_ipackets++;
|
|
|
|
|
|
|
|
/* Do IP checksum checking. */
|
2001-06-16 03:38:44 +00:00
|
|
|
if (extsts & NGE_RXEXTSTS_IPPKT)
|
|
|
|
m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
|
|
|
|
if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
|
|
|
|
m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
|
|
|
|
if ((extsts & NGE_RXEXTSTS_TCPPKT &&
|
|
|
|
!(extsts & NGE_RXEXTSTS_TCPCSUMERR)) ||
|
|
|
|
(extsts & NGE_RXEXTSTS_UDPPKT &&
|
|
|
|
!(extsts & NGE_RXEXTSTS_UDPCSUMERR))) {
|
|
|
|
m->m_pkthdr.csum_flags |=
|
|
|
|
CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
|
|
|
|
m->m_pkthdr.csum_data = 0xffff;
|
|
|
|
}
|
2001-05-11 19:56:39 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If we received a packet with a vlan tag, pass it
|
|
|
|
* to vlan_input() instead of ether_input().
|
|
|
|
*/
|
|
|
|
if (extsts & NGE_RXEXTSTS_VLANPKT) {
|
2002-11-14 23:54:55 +00:00
|
|
|
VLAN_INPUT_TAG(ifp, m,
|
2004-03-30 10:24:52 +00:00
|
|
|
ntohs(extsts & NGE_RXEXTSTS_VTCI), continue);
|
2002-11-14 23:54:55 +00:00
|
|
|
}
|
2001-05-11 19:56:39 +00:00
|
|
|
|
2002-11-14 23:54:55 +00:00
|
|
|
(*ifp->if_input)(ifp, m);
|
2001-05-11 19:56:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
sc->nge_cdata.nge_rx_prod = i;
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* A frame was downloaded to the chip. It's safe for us to clean up
|
|
|
|
* the list buffers.
|
|
|
|
*/
|
|
|
|
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_txeof(sc)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
{
|
|
|
|
struct nge_desc *cur_tx = NULL;
|
|
|
|
struct ifnet *ifp;
|
|
|
|
u_int32_t idx;
|
|
|
|
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
|
|
|
|
|
|
|
/* Clear the timeout timer. */
|
|
|
|
ifp->if_timer = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Go through our tx list and free mbufs for those
|
|
|
|
* frames that have been transmitted.
|
|
|
|
*/
|
|
|
|
idx = sc->nge_cdata.nge_tx_cons;
|
|
|
|
while (idx != sc->nge_cdata.nge_tx_prod) {
|
|
|
|
cur_tx = &sc->nge_ldata->nge_tx_list[idx];
|
|
|
|
|
|
|
|
if (NGE_OWNDESC(cur_tx))
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
|
|
|
|
sc->nge_cdata.nge_tx_cnt--;
|
|
|
|
NGE_INC(idx, NGE_TX_LIST_CNT);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
|
|
|
|
ifp->if_oerrors++;
|
|
|
|
if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
|
|
|
|
ifp->if_collisions++;
|
|
|
|
if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
|
|
|
|
ifp->if_collisions++;
|
|
|
|
}
|
|
|
|
|
|
|
|
ifp->if_collisions +=
|
|
|
|
(cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
|
|
|
|
|
|
|
|
ifp->if_opackets++;
|
|
|
|
if (cur_tx->nge_mbuf != NULL) {
|
|
|
|
m_freem(cur_tx->nge_mbuf);
|
|
|
|
cur_tx->nge_mbuf = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
sc->nge_cdata.nge_tx_cnt--;
|
|
|
|
NGE_INC(idx, NGE_TX_LIST_CNT);
|
|
|
|
ifp->if_timer = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
sc->nge_cdata.nge_tx_cons = idx;
|
|
|
|
|
|
|
|
if (cur_tx != NULL)
|
|
|
|
ifp->if_flags &= ~IFF_OACTIVE;
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_tick(xsc)
|
2001-05-11 19:56:39 +00:00
|
|
|
void *xsc;
|
|
|
|
{
|
|
|
|
struct nge_softc *sc;
|
|
|
|
struct mii_data *mii;
|
|
|
|
struct ifnet *ifp;
|
|
|
|
int s;
|
|
|
|
|
|
|
|
s = splimp();
|
|
|
|
|
|
|
|
sc = xsc;
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
|
|
|
|
2002-08-08 18:33:28 +00:00
|
|
|
if (sc->nge_tbi) {
|
|
|
|
if (!sc->nge_link) {
|
|
|
|
if (CSR_READ_4(sc, NGE_TBI_BMSR)
|
|
|
|
& NGE_TBIBMSR_ANEG_DONE) {
|
2001-05-11 19:56:39 +00:00
|
|
|
printf("nge%d: gigabit link up\n",
|
|
|
|
sc->nge_unit);
|
2002-08-08 18:33:28 +00:00
|
|
|
nge_miibus_statchg(sc->nge_miibus);
|
|
|
|
sc->nge_link++;
|
|
|
|
if (ifp->if_snd.ifq_head != NULL)
|
|
|
|
nge_start(ifp);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
mii = device_get_softc(sc->nge_miibus);
|
|
|
|
mii_tick(mii);
|
|
|
|
|
|
|
|
if (!sc->nge_link) {
|
|
|
|
if (mii->mii_media_status & IFM_ACTIVE &&
|
|
|
|
IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
|
|
|
|
sc->nge_link++;
|
|
|
|
if (IFM_SUBTYPE(mii->mii_media_active)
|
|
|
|
== IFM_1000_T)
|
|
|
|
printf("nge%d: gigabit link up\n",
|
|
|
|
sc->nge_unit);
|
|
|
|
if (ifp->if_snd.ifq_head != NULL)
|
|
|
|
nge_start(ifp);
|
|
|
|
}
|
2002-05-04 11:15:33 +00:00
|
|
|
}
|
2001-05-11 19:56:39 +00:00
|
|
|
}
|
2002-05-04 11:15:33 +00:00
|
|
|
sc->nge_stat_ch = timeout(nge_tick, sc, hz);
|
2001-05-11 19:56:39 +00:00
|
|
|
|
|
|
|
splx(s);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2002-11-06 15:50:32 +00:00
|
|
|
#ifdef DEVICE_POLLING
|
|
|
|
static poll_handler_t nge_poll;
|
|
|
|
|
|
|
|
static void
|
|
|
|
nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
|
|
|
|
{
|
|
|
|
struct nge_softc *sc = ifp->if_softc;
|
|
|
|
|
|
|
|
if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
|
|
|
|
CSR_WRITE_4(sc, NGE_IER, 1);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* On the nge, reading the status register also clears it.
|
|
|
|
* So before returning to intr mode we must make sure that all
|
|
|
|
* possible pending sources of interrupts have been served.
|
|
|
|
* In practice this means run to completion the *eof routines,
|
|
|
|
* and then call the interrupt routine
|
|
|
|
*/
|
|
|
|
sc->rxcycles = count;
|
|
|
|
nge_rxeof(sc);
|
|
|
|
nge_txeof(sc);
|
|
|
|
if (ifp->if_snd.ifq_head != NULL)
|
|
|
|
nge_start(ifp);
|
|
|
|
|
|
|
|
if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
|
|
|
|
u_int32_t status;
|
|
|
|
|
|
|
|
/* Reading the ISR register clears all interrupts. */
|
|
|
|
status = CSR_READ_4(sc, NGE_ISR);
|
|
|
|
|
|
|
|
if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW))
|
|
|
|
nge_rxeof(sc);
|
|
|
|
|
|
|
|
if (status & (NGE_ISR_RX_IDLE))
|
|
|
|
NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
|
|
|
|
|
|
|
|
if (status & NGE_ISR_SYSERR) {
|
|
|
|
nge_reset(sc);
|
|
|
|
nge_init(sc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* DEVICE_POLLING */
|
|
|
|
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_intr(arg)
|
2001-05-11 19:56:39 +00:00
|
|
|
void *arg;
|
|
|
|
{
|
|
|
|
struct nge_softc *sc;
|
|
|
|
struct ifnet *ifp;
|
|
|
|
u_int32_t status;
|
|
|
|
|
|
|
|
sc = arg;
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
|
|
|
|
2002-11-06 15:50:32 +00:00
|
|
|
#ifdef DEVICE_POLLING
|
2004-04-11 16:26:39 +00:00
|
|
|
if (ifp->if_flags & IFF_POLLING)
|
2002-11-06 15:50:32 +00:00
|
|
|
return;
|
|
|
|
if (ether_poll_register(nge_poll, ifp)) { /* ok, disable interrupts */
|
|
|
|
CSR_WRITE_4(sc, NGE_IER, 0);
|
|
|
|
nge_poll(ifp, 0, 1);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif /* DEVICE_POLLING */
|
|
|
|
|
2001-05-11 19:56:39 +00:00
|
|
|
/* Supress unwanted interrupts */
|
|
|
|
if (!(ifp->if_flags & IFF_UP)) {
|
|
|
|
nge_stop(sc);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Disable interrupts. */
|
|
|
|
CSR_WRITE_4(sc, NGE_IER, 0);
|
|
|
|
|
2002-08-08 18:33:28 +00:00
|
|
|
/* Data LED on for TBI mode */
|
|
|
|
if(sc->nge_tbi)
|
|
|
|
CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
|
|
|
|
| NGE_GPIO_GP3_OUT);
|
|
|
|
|
2001-05-11 19:56:39 +00:00
|
|
|
for (;;) {
|
|
|
|
/* Reading the ISR register clears all interrupts. */
|
|
|
|
status = CSR_READ_4(sc, NGE_ISR);
|
|
|
|
|
|
|
|
if ((status & NGE_INTRS) == 0)
|
|
|
|
break;
|
|
|
|
|
|
|
|
if ((status & NGE_ISR_TX_DESC_OK) ||
|
|
|
|
(status & NGE_ISR_TX_ERR) ||
|
|
|
|
(status & NGE_ISR_TX_OK) ||
|
|
|
|
(status & NGE_ISR_TX_IDLE))
|
|
|
|
nge_txeof(sc);
|
|
|
|
|
|
|
|
if ((status & NGE_ISR_RX_DESC_OK) ||
|
2001-07-16 16:35:09 +00:00
|
|
|
(status & NGE_ISR_RX_ERR) ||
|
2001-09-19 21:39:26 +00:00
|
|
|
(status & NGE_ISR_RX_OFLOW) ||
|
2002-04-13 21:33:33 +00:00
|
|
|
(status & NGE_ISR_RX_FIFO_OFLOW) ||
|
|
|
|
(status & NGE_ISR_RX_IDLE) ||
|
2001-05-11 19:56:39 +00:00
|
|
|
(status & NGE_ISR_RX_OK))
|
|
|
|
nge_rxeof(sc);
|
2002-04-13 21:33:33 +00:00
|
|
|
|
|
|
|
if ((status & NGE_ISR_RX_IDLE))
|
|
|
|
NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
|
|
|
|
|
2001-05-11 19:56:39 +00:00
|
|
|
if (status & NGE_ISR_SYSERR) {
|
|
|
|
nge_reset(sc);
|
|
|
|
ifp->if_flags &= ~IFF_RUNNING;
|
|
|
|
nge_init(sc);
|
|
|
|
}
|
|
|
|
|
2002-05-04 11:15:33 +00:00
|
|
|
#if 0
|
|
|
|
/*
|
|
|
|
* XXX: nge_tick() is not ready to be called this way
|
|
|
|
* it screws up the aneg timeout because mii_tick() is
|
|
|
|
* only to be called once per second.
|
|
|
|
*/
|
2001-05-11 19:56:39 +00:00
|
|
|
if (status & NGE_IMR_PHY_INTR) {
|
|
|
|
sc->nge_link = 0;
|
|
|
|
nge_tick(sc);
|
|
|
|
}
|
2002-05-04 11:15:33 +00:00
|
|
|
#endif
|
2001-05-11 19:56:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Re-enable interrupts. */
|
|
|
|
CSR_WRITE_4(sc, NGE_IER, 1);
|
|
|
|
|
|
|
|
if (ifp->if_snd.ifq_head != NULL)
|
|
|
|
nge_start(ifp);
|
|
|
|
|
2002-08-08 18:33:28 +00:00
|
|
|
/* Data LED off for TBI mode */
|
|
|
|
|
|
|
|
if(sc->nge_tbi)
|
|
|
|
CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
|
|
|
|
& ~NGE_GPIO_GP3_OUT);
|
|
|
|
|
2001-05-11 19:56:39 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
|
|
|
|
* pointers to the fragment pointers.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static int
|
|
|
|
nge_encap(sc, m_head, txidx)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
struct mbuf *m_head;
|
|
|
|
u_int32_t *txidx;
|
|
|
|
{
|
|
|
|
struct nge_desc *f = NULL;
|
|
|
|
struct mbuf *m;
|
|
|
|
int frag, cur, cnt = 0;
|
2002-11-14 23:54:55 +00:00
|
|
|
struct m_tag *mtag;
|
2001-05-11 19:56:39 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Start packing the mbufs in this chain into
|
|
|
|
* the fragment pointers. Stop when we run out
|
|
|
|
* of fragments or hit the end of the mbuf chain.
|
|
|
|
*/
|
|
|
|
m = m_head;
|
|
|
|
cur = frag = *txidx;
|
|
|
|
|
|
|
|
for (m = m_head; m != NULL; m = m->m_next) {
|
|
|
|
if (m->m_len != 0) {
|
|
|
|
if ((NGE_TX_LIST_CNT -
|
|
|
|
(sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
|
|
|
|
return(ENOBUFS);
|
|
|
|
f = &sc->nge_ldata->nge_tx_list[frag];
|
|
|
|
f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
|
|
|
|
f->nge_ptr = vtophys(mtod(m, vm_offset_t));
|
|
|
|
if (cnt != 0)
|
|
|
|
f->nge_ctl |= NGE_CMDSTS_OWN;
|
|
|
|
cur = frag;
|
|
|
|
NGE_INC(frag, NGE_TX_LIST_CNT);
|
|
|
|
cnt++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (m != NULL)
|
|
|
|
return(ENOBUFS);
|
|
|
|
|
2001-06-15 18:43:19 +00:00
|
|
|
sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
|
2001-05-11 19:56:39 +00:00
|
|
|
if (m_head->m_pkthdr.csum_flags) {
|
|
|
|
if (m_head->m_pkthdr.csum_flags & CSUM_IP)
|
2001-06-15 18:43:19 +00:00
|
|
|
sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
|
2001-05-11 19:56:39 +00:00
|
|
|
NGE_TXEXTSTS_IPCSUM;
|
|
|
|
if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
|
2001-06-15 18:43:19 +00:00
|
|
|
sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
|
2001-05-11 19:56:39 +00:00
|
|
|
NGE_TXEXTSTS_TCPCSUM;
|
|
|
|
if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
|
2001-06-15 18:43:19 +00:00
|
|
|
sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
|
2001-05-11 19:56:39 +00:00
|
|
|
NGE_TXEXTSTS_UDPCSUM;
|
|
|
|
}
|
|
|
|
|
2002-11-14 23:54:55 +00:00
|
|
|
mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m);
|
|
|
|
if (mtag != NULL) {
|
2001-05-11 19:56:39 +00:00
|
|
|
sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
|
2004-03-30 10:24:52 +00:00
|
|
|
(NGE_TXEXTSTS_VLANPKT|htons(VLAN_TAG_VALUE(mtag)));
|
2001-05-11 19:56:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
|
|
|
|
sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
|
|
|
|
sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
|
|
|
|
sc->nge_cdata.nge_tx_cnt += cnt;
|
|
|
|
*txidx = frag;
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Main transmit routine. To avoid having to do mbuf copies, we put pointers
|
|
|
|
* to the mbuf data regions directly in the transmit lists. We also save a
|
|
|
|
* copy of the pointers since the transmit list fragment pointers are
|
|
|
|
* physical addresses.
|
|
|
|
*/
|
|
|
|
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_start(ifp)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct ifnet *ifp;
|
|
|
|
{
|
|
|
|
struct nge_softc *sc;
|
|
|
|
struct mbuf *m_head = NULL;
|
|
|
|
u_int32_t idx;
|
|
|
|
|
|
|
|
sc = ifp->if_softc;
|
|
|
|
|
|
|
|
if (!sc->nge_link)
|
|
|
|
return;
|
|
|
|
|
|
|
|
idx = sc->nge_cdata.nge_tx_prod;
|
|
|
|
|
|
|
|
if (ifp->if_flags & IFF_OACTIVE)
|
|
|
|
return;
|
|
|
|
|
|
|
|
while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
|
|
|
|
IF_DEQUEUE(&ifp->if_snd, m_head);
|
|
|
|
if (m_head == NULL)
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (nge_encap(sc, m_head, &idx)) {
|
|
|
|
IF_PREPEND(&ifp->if_snd, m_head);
|
|
|
|
ifp->if_flags |= IFF_OACTIVE;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If there's a BPF listener, bounce a copy of this frame
|
|
|
|
* to him.
|
|
|
|
*/
|
2002-11-14 23:54:55 +00:00
|
|
|
BPF_MTAP(ifp, m_head);
|
2001-05-11 19:56:39 +00:00
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Transmit */
|
|
|
|
sc->nge_cdata.nge_tx_prod = idx;
|
|
|
|
NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set a timeout in case the chip goes out to lunch.
|
|
|
|
*/
|
|
|
|
ifp->if_timer = 5;
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_init(xsc)
|
2001-05-11 19:56:39 +00:00
|
|
|
void *xsc;
|
|
|
|
{
|
|
|
|
struct nge_softc *sc = xsc;
|
|
|
|
struct ifnet *ifp = &sc->arpcom.ac_if;
|
|
|
|
struct mii_data *mii;
|
|
|
|
int s;
|
|
|
|
|
|
|
|
if (ifp->if_flags & IFF_RUNNING)
|
|
|
|
return;
|
|
|
|
|
|
|
|
s = splimp();
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Cancel pending I/O and free all RX/TX buffers.
|
|
|
|
*/
|
|
|
|
nge_stop(sc);
|
|
|
|
|
2002-08-08 18:33:28 +00:00
|
|
|
if (sc->nge_tbi) {
|
|
|
|
mii = NULL;
|
|
|
|
} else {
|
|
|
|
mii = device_get_softc(sc->nge_miibus);
|
|
|
|
}
|
2001-05-11 19:56:39 +00:00
|
|
|
|
|
|
|
/* Set MAC address */
|
|
|
|
CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
|
|
|
|
CSR_WRITE_4(sc, NGE_RXFILT_DATA,
|
|
|
|
((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
|
|
|
|
CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
|
|
|
|
CSR_WRITE_4(sc, NGE_RXFILT_DATA,
|
|
|
|
((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
|
|
|
|
CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
|
|
|
|
CSR_WRITE_4(sc, NGE_RXFILT_DATA,
|
|
|
|
((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
|
|
|
|
|
|
|
|
/* Init circular RX list. */
|
|
|
|
if (nge_list_rx_init(sc) == ENOBUFS) {
|
|
|
|
printf("nge%d: initialization failed: no "
|
|
|
|
"memory for rx buffers\n", sc->nge_unit);
|
|
|
|
nge_stop(sc);
|
|
|
|
(void)splx(s);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Init tx descriptors.
|
|
|
|
*/
|
|
|
|
nge_list_tx_init(sc);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* For the NatSemi chip, we have to explicitly enable the
|
|
|
|
* reception of ARP frames, as well as turn on the 'perfect
|
|
|
|
* match' filter where we store the station address, otherwise
|
|
|
|
* we won't receive unicasts meant for this host.
|
|
|
|
*/
|
|
|
|
NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
|
|
|
|
NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
|
|
|
|
|
|
|
|
/* If we want promiscuous mode, set the allframes bit. */
|
|
|
|
if (ifp->if_flags & IFF_PROMISC) {
|
|
|
|
NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
|
|
|
|
} else {
|
|
|
|
NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set the capture broadcast bit to capture broadcast frames.
|
|
|
|
*/
|
|
|
|
if (ifp->if_flags & IFF_BROADCAST) {
|
|
|
|
NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
|
|
|
|
} else {
|
|
|
|
NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Load the multicast filter.
|
|
|
|
*/
|
|
|
|
nge_setmulti(sc);
|
|
|
|
|
|
|
|
/* Turn the receive filter on */
|
|
|
|
NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Load the address of the RX and TX lists.
|
|
|
|
*/
|
|
|
|
CSR_WRITE_4(sc, NGE_RX_LISTPTR,
|
|
|
|
vtophys(&sc->nge_ldata->nge_rx_list[0]));
|
|
|
|
CSR_WRITE_4(sc, NGE_TX_LISTPTR,
|
|
|
|
vtophys(&sc->nge_ldata->nge_tx_list[0]));
|
|
|
|
|
|
|
|
/* Set RX configuration */
|
|
|
|
CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
|
|
|
|
/*
|
|
|
|
* Enable hardware checksum validation for all IPv4
|
|
|
|
* packets, do not reject packets with bad checksums.
|
|
|
|
*/
|
2001-06-16 03:38:44 +00:00
|
|
|
CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
|
2001-05-11 19:56:39 +00:00
|
|
|
|
|
|
|
/*
|
2001-09-05 21:10:28 +00:00
|
|
|
* Tell the chip to detect and strip VLAN tag info from
|
|
|
|
* received frames. The tag will be provided in the extsts
|
|
|
|
* field in the RX descriptors.
|
2001-05-11 19:56:39 +00:00
|
|
|
*/
|
|
|
|
NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
|
|
|
|
NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
|
|
|
|
|
|
|
|
/* Set TX configuration */
|
|
|
|
CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable TX IPv4 checksumming on a per-packet basis.
|
|
|
|
*/
|
2001-06-16 03:38:44 +00:00
|
|
|
CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
|
2001-05-11 19:56:39 +00:00
|
|
|
|
|
|
|
/*
|
2001-09-05 21:10:28 +00:00
|
|
|
* Tell the chip to insert VLAN tags on a per-packet basis as
|
|
|
|
* dictated by the code in the frame encapsulation routine.
|
2001-05-11 19:56:39 +00:00
|
|
|
*/
|
|
|
|
NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
|
|
|
|
|
|
|
|
/* Set full/half duplex mode. */
|
2002-08-08 18:33:28 +00:00
|
|
|
if (sc->nge_tbi) {
|
|
|
|
if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
|
|
|
|
== IFM_FDX) {
|
|
|
|
NGE_SETBIT(sc, NGE_TX_CFG,
|
|
|
|
(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
|
|
|
|
NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
|
|
|
|
} else {
|
|
|
|
NGE_CLRBIT(sc, NGE_TX_CFG,
|
|
|
|
(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
|
|
|
|
NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
|
|
|
|
}
|
2001-05-11 19:56:39 +00:00
|
|
|
} else {
|
2002-08-08 18:33:28 +00:00
|
|
|
if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
|
|
|
|
NGE_SETBIT(sc, NGE_TX_CFG,
|
|
|
|
(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
|
|
|
|
NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
|
|
|
|
} else {
|
|
|
|
NGE_CLRBIT(sc, NGE_TX_CFG,
|
|
|
|
(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
|
|
|
|
NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
|
|
|
|
}
|
2001-05-11 19:56:39 +00:00
|
|
|
}
|
|
|
|
|
2002-05-04 11:15:33 +00:00
|
|
|
nge_tick(sc);
|
|
|
|
|
2001-05-11 19:56:39 +00:00
|
|
|
/*
|
|
|
|
* Enable the delivery of PHY interrupts based on
|
2001-06-06 22:16:23 +00:00
|
|
|
* link/speed/duplex status changes. Also enable the
|
|
|
|
* extsts field in the DMA descriptors (needed for
|
|
|
|
* TCP/IP checksum offload on transmit).
|
2001-05-11 19:56:39 +00:00
|
|
|
*/
|
2001-07-08 16:24:01 +00:00
|
|
|
NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD|
|
2001-06-06 22:16:23 +00:00
|
|
|
NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB);
|
2001-05-11 19:56:39 +00:00
|
|
|
|
2001-07-10 23:07:15 +00:00
|
|
|
/*
|
|
|
|
* Configure interrupt holdoff (moderation). We can
|
|
|
|
* have the chip delay interrupt delivery for a certain
|
|
|
|
* period. Units are in 100us, and the max setting
|
|
|
|
* is 25500us (0xFF x 100us). Default is a 100us holdoff.
|
|
|
|
*/
|
|
|
|
CSR_WRITE_4(sc, NGE_IHR, 0x01);
|
|
|
|
|
2001-05-11 19:56:39 +00:00
|
|
|
/*
|
|
|
|
* Enable interrupts.
|
|
|
|
*/
|
|
|
|
CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
|
2002-11-06 15:50:32 +00:00
|
|
|
#ifdef DEVICE_POLLING
|
|
|
|
/*
|
|
|
|
* ... only enable interrupts if we are not polling, make sure
|
|
|
|
* they are off otherwise.
|
|
|
|
*/
|
2004-04-11 16:26:39 +00:00
|
|
|
if (ifp->if_flags & IFF_POLLING)
|
2002-11-06 15:50:32 +00:00
|
|
|
CSR_WRITE_4(sc, NGE_IER, 0);
|
|
|
|
else
|
|
|
|
#endif /* DEVICE_POLLING */
|
2001-05-11 19:56:39 +00:00
|
|
|
CSR_WRITE_4(sc, NGE_IER, 1);
|
|
|
|
|
|
|
|
/* Enable receiver and transmitter. */
|
|
|
|
NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
|
|
|
|
NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
|
|
|
|
|
|
|
|
nge_ifmedia_upd(ifp);
|
|
|
|
|
|
|
|
ifp->if_flags |= IFF_RUNNING;
|
|
|
|
ifp->if_flags &= ~IFF_OACTIVE;
|
|
|
|
|
|
|
|
(void)splx(s);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set media options.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static int
|
|
|
|
nge_ifmedia_upd(ifp)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct ifnet *ifp;
|
|
|
|
{
|
|
|
|
struct nge_softc *sc;
|
|
|
|
struct mii_data *mii;
|
|
|
|
|
|
|
|
sc = ifp->if_softc;
|
|
|
|
|
2002-08-08 18:33:28 +00:00
|
|
|
if (sc->nge_tbi) {
|
|
|
|
if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
|
|
|
|
== IFM_AUTO) {
|
|
|
|
CSR_WRITE_4(sc, NGE_TBI_ANAR,
|
|
|
|
CSR_READ_4(sc, NGE_TBI_ANAR)
|
|
|
|
| NGE_TBIANAR_HDX | NGE_TBIANAR_FDX
|
|
|
|
| NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2);
|
|
|
|
CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
|
|
|
|
| NGE_TBIBMCR_RESTART_ANEG);
|
|
|
|
CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
|
|
|
|
} else if ((sc->nge_ifmedia.ifm_cur->ifm_media
|
|
|
|
& IFM_GMASK) == IFM_FDX) {
|
|
|
|
NGE_SETBIT(sc, NGE_TX_CFG,
|
|
|
|
(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
|
|
|
|
NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
|
|
|
|
|
|
|
|
CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
|
|
|
|
CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
|
|
|
|
} else {
|
|
|
|
NGE_CLRBIT(sc, NGE_TX_CFG,
|
|
|
|
(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
|
|
|
|
NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
|
|
|
|
|
|
|
|
CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
|
|
|
|
CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
|
|
|
|
& ~NGE_GPIO_GP3_OUT);
|
|
|
|
} else {
|
|
|
|
mii = device_get_softc(sc->nge_miibus);
|
|
|
|
sc->nge_link = 0;
|
|
|
|
if (mii->mii_instance) {
|
|
|
|
struct mii_softc *miisc;
|
|
|
|
for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
|
|
|
|
miisc = LIST_NEXT(miisc, mii_list))
|
|
|
|
mii_phy_reset(miisc);
|
|
|
|
}
|
|
|
|
mii_mediachg(mii);
|
2001-05-11 19:56:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Report current media status.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_ifmedia_sts(ifp, ifmr)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct ifnet *ifp;
|
|
|
|
struct ifmediareq *ifmr;
|
|
|
|
{
|
|
|
|
struct nge_softc *sc;
|
|
|
|
struct mii_data *mii;
|
|
|
|
|
|
|
|
sc = ifp->if_softc;
|
|
|
|
|
2002-08-08 18:33:28 +00:00
|
|
|
if (sc->nge_tbi) {
|
|
|
|
ifmr->ifm_status = IFM_AVALID;
|
|
|
|
ifmr->ifm_active = IFM_ETHER;
|
|
|
|
|
|
|
|
if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
|
|
|
|
ifmr->ifm_status |= IFM_ACTIVE;
|
|
|
|
}
|
|
|
|
if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
|
|
|
|
ifmr->ifm_active |= IFM_LOOP;
|
|
|
|
if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
|
|
|
|
ifmr->ifm_active |= IFM_NONE;
|
|
|
|
ifmr->ifm_status = 0;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
ifmr->ifm_active |= IFM_1000_SX;
|
|
|
|
if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
|
|
|
|
== IFM_AUTO) {
|
|
|
|
ifmr->ifm_active |= IFM_AUTO;
|
|
|
|
if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
|
|
|
|
& NGE_TBIANAR_FDX) {
|
|
|
|
ifmr->ifm_active |= IFM_FDX;
|
|
|
|
}else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
|
|
|
|
& NGE_TBIANAR_HDX) {
|
|
|
|
ifmr->ifm_active |= IFM_HDX;
|
|
|
|
}
|
|
|
|
} else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
|
|
|
|
== IFM_FDX)
|
|
|
|
ifmr->ifm_active |= IFM_FDX;
|
|
|
|
else
|
|
|
|
ifmr->ifm_active |= IFM_HDX;
|
|
|
|
|
|
|
|
} else {
|
|
|
|
mii = device_get_softc(sc->nge_miibus);
|
|
|
|
mii_pollstat(mii);
|
|
|
|
ifmr->ifm_active = mii->mii_media_active;
|
|
|
|
ifmr->ifm_status = mii->mii_media_status;
|
|
|
|
}
|
2001-05-11 19:56:39 +00:00
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2002-07-06 15:59:57 +00:00
|
|
|
static int
|
|
|
|
nge_ioctl(ifp, command, data)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct ifnet *ifp;
|
|
|
|
u_long command;
|
|
|
|
caddr_t data;
|
|
|
|
{
|
|
|
|
struct nge_softc *sc = ifp->if_softc;
|
|
|
|
struct ifreq *ifr = (struct ifreq *) data;
|
|
|
|
struct mii_data *mii;
|
|
|
|
int s, error = 0;
|
|
|
|
|
|
|
|
s = splimp();
|
|
|
|
|
|
|
|
switch(command) {
|
|
|
|
case SIOCSIFMTU:
|
|
|
|
if (ifr->ifr_mtu > NGE_JUMBO_MTU)
|
|
|
|
error = EINVAL;
|
2001-06-16 03:38:44 +00:00
|
|
|
else {
|
2001-05-11 19:56:39 +00:00
|
|
|
ifp->if_mtu = ifr->ifr_mtu;
|
2001-06-16 03:38:44 +00:00
|
|
|
/*
|
|
|
|
* Workaround: if the MTU is larger than
|
|
|
|
* 8152 (TX FIFO size minus 64 minus 18), turn off
|
|
|
|
* TX checksum offloading.
|
|
|
|
*/
|
2001-06-16 04:02:37 +00:00
|
|
|
if (ifr->ifr_mtu >= 8152)
|
2001-06-16 03:38:44 +00:00
|
|
|
ifp->if_hwassist = 0;
|
|
|
|
else
|
|
|
|
ifp->if_hwassist = NGE_CSUM_FEATURES;
|
|
|
|
}
|
2001-05-11 19:56:39 +00:00
|
|
|
break;
|
|
|
|
case SIOCSIFFLAGS:
|
|
|
|
if (ifp->if_flags & IFF_UP) {
|
|
|
|
if (ifp->if_flags & IFF_RUNNING &&
|
|
|
|
ifp->if_flags & IFF_PROMISC &&
|
|
|
|
!(sc->nge_if_flags & IFF_PROMISC)) {
|
|
|
|
NGE_SETBIT(sc, NGE_RXFILT_CTL,
|
|
|
|
NGE_RXFILTCTL_ALLPHYS|
|
|
|
|
NGE_RXFILTCTL_ALLMULTI);
|
|
|
|
} else if (ifp->if_flags & IFF_RUNNING &&
|
|
|
|
!(ifp->if_flags & IFF_PROMISC) &&
|
|
|
|
sc->nge_if_flags & IFF_PROMISC) {
|
|
|
|
NGE_CLRBIT(sc, NGE_RXFILT_CTL,
|
|
|
|
NGE_RXFILTCTL_ALLPHYS);
|
|
|
|
if (!(ifp->if_flags & IFF_ALLMULTI))
|
|
|
|
NGE_CLRBIT(sc, NGE_RXFILT_CTL,
|
|
|
|
NGE_RXFILTCTL_ALLMULTI);
|
|
|
|
} else {
|
|
|
|
ifp->if_flags &= ~IFF_RUNNING;
|
|
|
|
nge_init(sc);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (ifp->if_flags & IFF_RUNNING)
|
|
|
|
nge_stop(sc);
|
|
|
|
}
|
|
|
|
sc->nge_if_flags = ifp->if_flags;
|
|
|
|
error = 0;
|
|
|
|
break;
|
|
|
|
case SIOCADDMULTI:
|
|
|
|
case SIOCDELMULTI:
|
|
|
|
nge_setmulti(sc);
|
|
|
|
error = 0;
|
|
|
|
break;
|
|
|
|
case SIOCGIFMEDIA:
|
|
|
|
case SIOCSIFMEDIA:
|
2002-08-08 18:33:28 +00:00
|
|
|
if (sc->nge_tbi) {
|
|
|
|
error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia,
|
|
|
|
command);
|
|
|
|
} else {
|
|
|
|
mii = device_get_softc(sc->nge_miibus);
|
|
|
|
error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
|
|
|
|
command);
|
|
|
|
}
|
2001-05-11 19:56:39 +00:00
|
|
|
break;
|
|
|
|
default:
|
2002-11-14 23:54:55 +00:00
|
|
|
error = ether_ioctl(ifp, command, data);
|
2001-05-11 19:56:39 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
(void)splx(s);
|
|
|
|
|
|
|
|
return(error);
|
|
|
|
}
|
|
|
|
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_watchdog(ifp)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct ifnet *ifp;
|
|
|
|
{
|
|
|
|
struct nge_softc *sc;
|
|
|
|
|
|
|
|
sc = ifp->if_softc;
|
|
|
|
|
|
|
|
ifp->if_oerrors++;
|
|
|
|
printf("nge%d: watchdog timeout\n", sc->nge_unit);
|
|
|
|
|
|
|
|
nge_stop(sc);
|
|
|
|
nge_reset(sc);
|
|
|
|
ifp->if_flags &= ~IFF_RUNNING;
|
|
|
|
nge_init(sc);
|
|
|
|
|
|
|
|
if (ifp->if_snd.ifq_head != NULL)
|
|
|
|
nge_start(ifp);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Stop the adapter and free any mbufs allocated to the
|
|
|
|
* RX and TX lists.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_stop(sc)
|
2001-05-11 19:56:39 +00:00
|
|
|
struct nge_softc *sc;
|
|
|
|
{
|
|
|
|
register int i;
|
|
|
|
struct ifnet *ifp;
|
|
|
|
struct mii_data *mii;
|
|
|
|
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
|
|
|
ifp->if_timer = 0;
|
2002-08-08 18:33:28 +00:00
|
|
|
if (sc->nge_tbi) {
|
|
|
|
mii = NULL;
|
|
|
|
} else {
|
|
|
|
mii = device_get_softc(sc->nge_miibus);
|
|
|
|
}
|
2001-05-11 19:56:39 +00:00
|
|
|
|
|
|
|
untimeout(nge_tick, sc, sc->nge_stat_ch);
|
2002-11-06 15:50:32 +00:00
|
|
|
#ifdef DEVICE_POLLING
|
|
|
|
ether_poll_deregister(ifp);
|
|
|
|
#endif
|
2001-05-11 19:56:39 +00:00
|
|
|
CSR_WRITE_4(sc, NGE_IER, 0);
|
|
|
|
CSR_WRITE_4(sc, NGE_IMR, 0);
|
|
|
|
NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
|
|
|
|
DELAY(1000);
|
|
|
|
CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
|
|
|
|
CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
|
|
|
|
|
2002-08-08 18:33:28 +00:00
|
|
|
if (!sc->nge_tbi)
|
|
|
|
mii_down(mii);
|
2001-05-11 19:56:39 +00:00
|
|
|
|
|
|
|
sc->nge_link = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Free data in the RX lists.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < NGE_RX_LIST_CNT; i++) {
|
|
|
|
if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
|
|
|
|
m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
|
|
|
|
sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
bzero((char *)&sc->nge_ldata->nge_rx_list,
|
|
|
|
sizeof(sc->nge_ldata->nge_rx_list));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Free the TX list buffers.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < NGE_TX_LIST_CNT; i++) {
|
|
|
|
if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
|
|
|
|
m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
|
|
|
|
sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
bzero((char *)&sc->nge_ldata->nge_tx_list,
|
|
|
|
sizeof(sc->nge_ldata->nge_tx_list));
|
|
|
|
|
|
|
|
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Stop all chip I/O so that the kernel's probe routines don't
|
|
|
|
* get confused by errant DMAs when rebooting.
|
|
|
|
*/
|
2002-07-06 15:59:57 +00:00
|
|
|
static void
|
|
|
|
nge_shutdown(dev)
|
2001-05-11 19:56:39 +00:00
|
|
|
device_t dev;
|
|
|
|
{
|
|
|
|
struct nge_softc *sc;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
nge_reset(sc);
|
|
|
|
nge_stop(sc);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|