2013-11-11 16:14:25 +00:00
|
|
|
/*-
|
|
|
|
* Copyright (c) 2008-2012 Semihalf.
|
|
|
|
* All rights reserved.
|
|
|
|
*
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
* modification, are permitted provided that the following conditions
|
|
|
|
* are met:
|
|
|
|
*
|
|
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer.
|
|
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
|
|
* documentation and/or other materials provided with the distribution.
|
|
|
|
*
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
|
|
|
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
|
|
|
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
|
|
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
|
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
|
|
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
|
|
|
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
*/
|
|
|
|
|
2015-12-30 03:43:25 +00:00
|
|
|
#include "opt_platform.h"
|
2013-11-11 16:14:25 +00:00
|
|
|
#include <sys/cdefs.h>
|
|
|
|
__FBSDID("$FreeBSD$");
|
|
|
|
|
|
|
|
#include <sys/param.h>
|
|
|
|
#include <sys/systm.h>
|
|
|
|
#include <sys/kernel.h>
|
|
|
|
#include <sys/bus.h>
|
|
|
|
#include <sys/pcpu.h>
|
|
|
|
#include <sys/proc.h>
|
|
|
|
#include <sys/smp.h>
|
|
|
|
|
|
|
|
#include <machine/bus.h>
|
|
|
|
#include <machine/cpu.h>
|
|
|
|
#include <machine/hid.h>
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
#include <machine/_inttypes.h>
|
2015-12-30 03:43:25 +00:00
|
|
|
#include <machine/machdep.h>
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
#include <machine/md_var.h>
|
2013-11-11 16:14:25 +00:00
|
|
|
#include <machine/platform.h>
|
|
|
|
#include <machine/platformvar.h>
|
|
|
|
#include <machine/smp.h>
|
|
|
|
#include <machine/spr.h>
|
|
|
|
#include <machine/vmparam.h>
|
|
|
|
|
|
|
|
#include <dev/fdt/fdt_common.h>
|
|
|
|
#include <dev/ofw/ofw_bus.h>
|
|
|
|
#include <dev/ofw/ofw_bus_subr.h>
|
|
|
|
#include <dev/ofw/openfirm.h>
|
|
|
|
|
2013-11-17 02:03:36 +00:00
|
|
|
#include <vm/vm.h>
|
|
|
|
#include <vm/pmap.h>
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
#include <vm/vm_extern.h>
|
2013-11-17 02:03:36 +00:00
|
|
|
|
2013-11-11 16:14:25 +00:00
|
|
|
#include <powerpc/mpc85xx/mpc85xx.h>
|
|
|
|
|
|
|
|
#include "platform_if.h"
|
|
|
|
|
|
|
|
#ifdef SMP
|
|
|
|
extern void *ap_pcpu;
|
|
|
|
extern vm_paddr_t kernload; /* Kernel physical load address */
|
|
|
|
extern uint8_t __boot_page[]; /* Boot page body */
|
2016-04-19 01:48:18 +00:00
|
|
|
extern uint32_t bp_kernload;
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
|
|
|
|
struct cpu_release {
|
|
|
|
uint32_t entry_h;
|
|
|
|
uint32_t entry_l;
|
|
|
|
uint32_t r3_h;
|
|
|
|
uint32_t r3_l;
|
|
|
|
uint32_t reserved;
|
|
|
|
uint32_t pir;
|
|
|
|
};
|
2013-11-11 16:14:25 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
extern uint32_t *bootinfo;
|
2016-11-16 05:24:42 +00:00
|
|
|
vm_paddr_t ccsrbar_pa;
|
2013-11-17 02:03:36 +00:00
|
|
|
vm_offset_t ccsrbar_va;
|
2016-11-16 05:24:42 +00:00
|
|
|
vm_size_t ccsrbar_size;
|
2013-11-11 16:14:25 +00:00
|
|
|
|
|
|
|
static int cpu, maxcpu;
|
|
|
|
|
|
|
|
static int mpc85xx_probe(platform_t);
|
2013-12-01 19:43:15 +00:00
|
|
|
static void mpc85xx_mem_regions(platform_t, struct mem_region *phys,
|
|
|
|
int *physsz, struct mem_region *avail, int *availsz);
|
2013-11-11 16:14:25 +00:00
|
|
|
static u_long mpc85xx_timebase_freq(platform_t, struct cpuref *cpuref);
|
|
|
|
static int mpc85xx_smp_first_cpu(platform_t, struct cpuref *cpuref);
|
|
|
|
static int mpc85xx_smp_next_cpu(platform_t, struct cpuref *cpuref);
|
|
|
|
static int mpc85xx_smp_get_bsp(platform_t, struct cpuref *cpuref);
|
|
|
|
static int mpc85xx_smp_start_cpu(platform_t, struct pcpu *cpu);
|
2017-11-25 21:59:59 +00:00
|
|
|
static void mpc85xx_smp_timebase_sync(platform_t, u_long tb, int ap);
|
2016-01-01 02:47:40 +00:00
|
|
|
static void mpc85xx_idle(platform_t, int cpu);
|
|
|
|
static int mpc85xx_idle_wakeup(platform_t plat, int cpu);
|
2013-11-11 16:14:25 +00:00
|
|
|
|
|
|
|
static void mpc85xx_reset(platform_t);
|
|
|
|
|
|
|
|
static platform_method_t mpc85xx_methods[] = {
|
|
|
|
PLATFORMMETHOD(platform_probe, mpc85xx_probe),
|
|
|
|
PLATFORMMETHOD(platform_attach, mpc85xx_attach),
|
|
|
|
PLATFORMMETHOD(platform_mem_regions, mpc85xx_mem_regions),
|
|
|
|
PLATFORMMETHOD(platform_timebase_freq, mpc85xx_timebase_freq),
|
|
|
|
|
|
|
|
PLATFORMMETHOD(platform_smp_first_cpu, mpc85xx_smp_first_cpu),
|
|
|
|
PLATFORMMETHOD(platform_smp_next_cpu, mpc85xx_smp_next_cpu),
|
|
|
|
PLATFORMMETHOD(platform_smp_get_bsp, mpc85xx_smp_get_bsp),
|
|
|
|
PLATFORMMETHOD(platform_smp_start_cpu, mpc85xx_smp_start_cpu),
|
2017-11-25 21:59:59 +00:00
|
|
|
PLATFORMMETHOD(platform_smp_timebase_sync, mpc85xx_smp_timebase_sync),
|
2013-11-11 16:14:25 +00:00
|
|
|
|
|
|
|
PLATFORMMETHOD(platform_reset, mpc85xx_reset),
|
2016-01-01 02:47:40 +00:00
|
|
|
PLATFORMMETHOD(platform_idle, mpc85xx_idle),
|
|
|
|
PLATFORMMETHOD(platform_idle_wakeup, mpc85xx_idle_wakeup),
|
2013-11-11 16:14:25 +00:00
|
|
|
|
|
|
|
PLATFORMMETHOD_END
|
|
|
|
};
|
|
|
|
|
2015-08-22 03:29:12 +00:00
|
|
|
DEFINE_CLASS_0(mpc85xx, mpc85xx_platform, mpc85xx_methods, 0);
|
2013-11-11 16:14:25 +00:00
|
|
|
|
|
|
|
PLATFORM_DEF(mpc85xx_platform);
|
|
|
|
|
|
|
|
static int
|
|
|
|
mpc85xx_probe(platform_t plat)
|
|
|
|
{
|
2016-08-30 02:09:40 +00:00
|
|
|
u_int pvr = (mfpvr() >> 16) & 0xFFFF;
|
|
|
|
|
|
|
|
switch (pvr) {
|
|
|
|
case FSL_E500v1:
|
|
|
|
case FSL_E500v2:
|
|
|
|
case FSL_E500mc:
|
|
|
|
case FSL_E5500:
|
|
|
|
case FSL_E6500:
|
|
|
|
return (BUS_PROBE_DEFAULT);
|
|
|
|
}
|
2013-11-11 16:14:25 +00:00
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
|
2015-08-22 03:29:12 +00:00
|
|
|
int
|
2013-11-11 16:14:25 +00:00
|
|
|
mpc85xx_attach(platform_t plat)
|
|
|
|
{
|
2013-11-17 02:03:36 +00:00
|
|
|
phandle_t cpus, child, ccsr;
|
|
|
|
const char *soc_name_guesses[] = {"/soc", "soc", NULL};
|
|
|
|
const char **name;
|
|
|
|
pcell_t ranges[6], acells, pacells, scells;
|
|
|
|
uint64_t ccsrbar, ccsrsize;
|
2016-08-30 02:09:40 +00:00
|
|
|
int i;
|
2013-11-11 16:14:25 +00:00
|
|
|
|
|
|
|
if ((cpus = OF_finddevice("/cpus")) != -1) {
|
|
|
|
for (maxcpu = 0, child = OF_child(cpus); child != 0;
|
|
|
|
child = OF_peer(child), maxcpu++)
|
|
|
|
;
|
|
|
|
} else
|
|
|
|
maxcpu = 1;
|
|
|
|
|
2013-11-17 02:03:36 +00:00
|
|
|
/*
|
|
|
|
* Locate CCSR region. Irritatingly, there is no way to find it
|
|
|
|
* unless you already know where it is. Try to infer its location
|
|
|
|
* from the device tree.
|
|
|
|
*/
|
|
|
|
|
|
|
|
ccsr = -1;
|
|
|
|
for (name = soc_name_guesses; *name != NULL && ccsr == -1; name++)
|
|
|
|
ccsr = OF_finddevice(*name);
|
|
|
|
if (ccsr == -1) {
|
|
|
|
char type[64];
|
|
|
|
|
|
|
|
/* That didn't work. Search for devices of type "soc" */
|
|
|
|
child = OF_child(OF_peer(0));
|
|
|
|
for (OF_child(child); child != 0; child = OF_peer(child)) {
|
|
|
|
if (OF_getprop(child, "device_type", type, sizeof(type))
|
|
|
|
<= 0)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (strcmp(type, "soc") == 0) {
|
|
|
|
ccsr = child;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ccsr == -1)
|
|
|
|
panic("Could not locate CCSR window!");
|
|
|
|
|
|
|
|
OF_getprop(ccsr, "#size-cells", &scells, sizeof(scells));
|
|
|
|
OF_getprop(ccsr, "#address-cells", &acells, sizeof(acells));
|
|
|
|
OF_searchprop(OF_parent(ccsr), "#address-cells", &pacells,
|
|
|
|
sizeof(pacells));
|
|
|
|
OF_getprop(ccsr, "ranges", ranges, sizeof(ranges));
|
|
|
|
ccsrbar = ccsrsize = 0;
|
|
|
|
for (i = acells; i < acells + pacells; i++) {
|
|
|
|
ccsrbar <<= 32;
|
|
|
|
ccsrbar |= ranges[i];
|
|
|
|
}
|
|
|
|
for (i = acells + pacells; i < acells + pacells + scells; i++) {
|
|
|
|
ccsrsize <<= 32;
|
|
|
|
ccsrsize |= ranges[i];
|
|
|
|
}
|
|
|
|
ccsrbar_va = pmap_early_io_map(ccsrbar, ccsrsize);
|
2016-11-16 05:24:42 +00:00
|
|
|
ccsrbar_pa = ccsrbar;
|
|
|
|
ccsrbar_size = ccsrsize;
|
2013-11-17 02:03:36 +00:00
|
|
|
|
2016-09-07 04:13:28 +00:00
|
|
|
#if 0
|
2015-12-30 03:43:25 +00:00
|
|
|
mpc85xx_fix_errata(ccsrbar_va);
|
2016-09-07 04:13:28 +00:00
|
|
|
#endif
|
2015-12-30 03:43:25 +00:00
|
|
|
mpc85xx_enable_l3_cache();
|
|
|
|
|
2013-11-11 16:14:25 +00:00
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2013-12-01 19:43:15 +00:00
|
|
|
mpc85xx_mem_regions(platform_t plat, struct mem_region *phys, int *physsz,
|
|
|
|
struct mem_region *avail, int *availsz)
|
2013-11-11 16:14:25 +00:00
|
|
|
{
|
|
|
|
|
|
|
|
ofw_mem_regions(phys, physsz, avail, availsz);
|
|
|
|
}
|
|
|
|
|
|
|
|
static u_long
|
|
|
|
mpc85xx_timebase_freq(platform_t plat, struct cpuref *cpuref)
|
|
|
|
{
|
|
|
|
u_long ticks;
|
|
|
|
phandle_t cpus, child;
|
|
|
|
pcell_t freq;
|
|
|
|
|
|
|
|
if (bootinfo != NULL) {
|
|
|
|
if (bootinfo[0] == 1) {
|
|
|
|
/* Backward compatibility. See 8-STABLE. */
|
|
|
|
ticks = bootinfo[3] >> 3;
|
|
|
|
} else {
|
|
|
|
/* Compatibility with Juniper's loader. */
|
|
|
|
ticks = bootinfo[5] >> 3;
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
ticks = 0;
|
|
|
|
|
|
|
|
if ((cpus = OF_finddevice("/cpus")) == -1)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
if ((child = OF_child(cpus)) == 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
switch (OF_getproplen(child, "timebase-frequency")) {
|
|
|
|
case 4:
|
|
|
|
{
|
|
|
|
uint32_t tbase;
|
|
|
|
OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
|
|
|
|
ticks = tbase;
|
|
|
|
return (ticks);
|
|
|
|
}
|
|
|
|
case 8:
|
|
|
|
{
|
|
|
|
uint64_t tbase;
|
|
|
|
OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
|
|
|
|
ticks = tbase;
|
|
|
|
return (ticks);
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
freq = 0;
|
|
|
|
if (OF_getprop(child, "bus-frequency", (void *)&freq,
|
|
|
|
sizeof(freq)) <= 0)
|
|
|
|
goto out;
|
|
|
|
|
2016-08-03 01:22:11 +00:00
|
|
|
if (freq == 0)
|
|
|
|
goto out;
|
|
|
|
|
2013-11-11 16:14:25 +00:00
|
|
|
/*
|
|
|
|
* Time Base and Decrementer are updated every 8 CCB bus clocks.
|
|
|
|
* HID0[SEL_TBCLK] = 0
|
|
|
|
*/
|
2016-08-03 01:22:11 +00:00
|
|
|
if (mpc85xx_is_qoriq())
|
2015-12-30 03:43:25 +00:00
|
|
|
ticks = freq / 32;
|
2016-08-03 01:22:11 +00:00
|
|
|
else
|
2013-11-11 16:14:25 +00:00
|
|
|
ticks = freq / 8;
|
|
|
|
|
|
|
|
out:
|
|
|
|
if (ticks <= 0)
|
|
|
|
panic("Unable to determine timebase frequency!");
|
|
|
|
|
|
|
|
return (ticks);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mpc85xx_smp_first_cpu(platform_t plat, struct cpuref *cpuref)
|
|
|
|
{
|
|
|
|
|
|
|
|
cpu = 0;
|
|
|
|
cpuref->cr_cpuid = cpu;
|
|
|
|
cpuref->cr_hwref = cpuref->cr_cpuid;
|
|
|
|
if (bootverbose)
|
|
|
|
printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid);
|
|
|
|
cpu++;
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mpc85xx_smp_next_cpu(platform_t plat, struct cpuref *cpuref)
|
|
|
|
{
|
|
|
|
|
|
|
|
if (cpu >= maxcpu)
|
|
|
|
return (ENOENT);
|
|
|
|
|
|
|
|
cpuref->cr_cpuid = cpu++;
|
|
|
|
cpuref->cr_hwref = cpuref->cr_cpuid;
|
|
|
|
if (bootverbose)
|
|
|
|
printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mpc85xx_smp_get_bsp(platform_t plat, struct cpuref *cpuref)
|
|
|
|
{
|
|
|
|
|
|
|
|
cpuref->cr_cpuid = mfspr(SPR_PIR);
|
|
|
|
cpuref->cr_hwref = cpuref->cr_cpuid;
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
#ifdef SMP
|
|
|
|
static int
|
|
|
|
mpc85xx_smp_start_cpu_epapr(platform_t plat, struct pcpu *pc)
|
|
|
|
{
|
|
|
|
vm_paddr_t rel_pa, bptr;
|
|
|
|
volatile struct cpu_release *rel;
|
|
|
|
vm_offset_t rel_va, rel_page;
|
|
|
|
phandle_t node;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* If we're calling this, the node already exists. */
|
|
|
|
node = OF_finddevice("/cpus");
|
|
|
|
for (i = 0, node = OF_child(node); i < pc->pc_cpuid;
|
|
|
|
i++, node = OF_peer(node))
|
|
|
|
;
|
|
|
|
if (OF_getencprop(node, "cpu-release-addr", (pcell_t *)&rel_pa,
|
|
|
|
sizeof(rel_pa)) == -1) {
|
|
|
|
return (ENOENT);
|
|
|
|
}
|
|
|
|
|
|
|
|
rel_page = kva_alloc(PAGE_SIZE);
|
|
|
|
if (rel_page == 0)
|
|
|
|
return (ENOMEM);
|
|
|
|
|
|
|
|
critical_enter();
|
|
|
|
rel_va = rel_page + (rel_pa & PAGE_MASK);
|
|
|
|
pmap_kenter(rel_page, rel_pa & ~PAGE_MASK);
|
|
|
|
rel = (struct cpu_release *)rel_va;
|
|
|
|
bptr = ((vm_paddr_t)(uintptr_t)__boot_page - KERNBASE) + kernload;
|
|
|
|
cpu_flush_dcache(__DEVOLATILE(struct cpu_release *,rel), sizeof(*rel));
|
|
|
|
rel->pir = pc->pc_cpuid; __asm __volatile("sync");
|
|
|
|
rel->entry_h = (bptr >> 32);
|
|
|
|
rel->entry_l = bptr; __asm __volatile("sync");
|
|
|
|
cpu_flush_dcache(__DEVOLATILE(struct cpu_release *,rel), sizeof(*rel));
|
|
|
|
if (bootverbose)
|
|
|
|
printf("Waking up CPU %d via CPU release page %p\n",
|
|
|
|
pc->pc_cpuid, rel);
|
|
|
|
critical_exit();
|
|
|
|
pmap_kremove(rel_page);
|
|
|
|
kva_free(rel_page, PAGE_SIZE);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2013-11-11 16:14:25 +00:00
|
|
|
static int
|
|
|
|
mpc85xx_smp_start_cpu(platform_t plat, struct pcpu *pc)
|
|
|
|
{
|
|
|
|
#ifdef SMP
|
2015-12-30 03:43:25 +00:00
|
|
|
vm_paddr_t bptr;
|
|
|
|
uint32_t reg;
|
2016-04-19 01:48:18 +00:00
|
|
|
int timeout;
|
2015-12-30 03:43:25 +00:00
|
|
|
uintptr_t brr;
|
|
|
|
int cpuid;
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
int epapr_boot = 0;
|
2015-12-30 03:43:25 +00:00
|
|
|
uint32_t tgt;
|
2013-11-11 16:14:25 +00:00
|
|
|
|
2016-08-03 01:22:11 +00:00
|
|
|
if (mpc85xx_is_qoriq()) {
|
|
|
|
reg = ccsr_read4(OCP85XX_COREDISR);
|
|
|
|
cpuid = pc->pc_cpuid;
|
2015-12-30 03:43:25 +00:00
|
|
|
|
2016-08-03 01:22:11 +00:00
|
|
|
if ((reg & (1 << cpuid)) != 0) {
|
|
|
|
printf("%s: CPU %d is disabled!\n", __func__, pc->pc_cpuid);
|
|
|
|
return (-1);
|
|
|
|
}
|
2015-12-30 03:43:25 +00:00
|
|
|
|
2016-08-03 01:22:11 +00:00
|
|
|
brr = OCP85XX_BRR;
|
|
|
|
} else {
|
|
|
|
brr = OCP85XX_EEBPCR;
|
|
|
|
cpuid = pc->pc_cpuid + 24;
|
|
|
|
}
|
2016-04-19 01:48:18 +00:00
|
|
|
bp_kernload = kernload;
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
/*
|
|
|
|
* bp_kernload is in the boot page. Sync the cache because ePAPR
|
|
|
|
* booting has the other core(s) already running.
|
|
|
|
*/
|
2016-08-14 03:49:37 +00:00
|
|
|
cpu_flush_dcache(&bp_kernload, sizeof(bp_kernload));
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
|
|
|
|
ap_pcpu = pc;
|
|
|
|
__asm __volatile("msync; isync");
|
|
|
|
|
|
|
|
/* First try the ePAPR way. */
|
|
|
|
if (mpc85xx_smp_start_cpu_epapr(plat, pc) == 0) {
|
|
|
|
epapr_boot = 1;
|
|
|
|
goto spin_wait;
|
|
|
|
}
|
2016-08-03 01:22:11 +00:00
|
|
|
|
2015-12-30 03:43:25 +00:00
|
|
|
reg = ccsr_read4(brr);
|
|
|
|
if ((reg & (1 << cpuid)) != 0) {
|
2013-11-11 16:14:25 +00:00
|
|
|
printf("SMP: CPU %d already out of hold-off state!\n",
|
|
|
|
pc->pc_cpuid);
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
|
2015-12-30 03:43:25 +00:00
|
|
|
/* Flush caches to have our changes hit DRAM. */
|
|
|
|
cpu_flush_dcache(__boot_page, 4096);
|
|
|
|
|
|
|
|
bptr = ((vm_paddr_t)(uintptr_t)__boot_page - KERNBASE) + kernload;
|
|
|
|
KASSERT((bptr & 0xfff) == 0,
|
|
|
|
("%s: boot page is not aligned (%#jx)", __func__, (uintmax_t)bptr));
|
2016-08-03 01:22:11 +00:00
|
|
|
if (mpc85xx_is_qoriq()) {
|
|
|
|
/*
|
|
|
|
* Read DDR controller configuration to select proper BPTR target ID.
|
|
|
|
*
|
|
|
|
* On P5020 bit 29 of DDR1_CS0_CONFIG enables DDR controllers
|
|
|
|
* interleaving. If this bit is set, we have to use
|
|
|
|
* OCP85XX_TGTIF_RAM_INTL as BPTR target ID. On other QorIQ DPAA SoCs,
|
|
|
|
* this bit is reserved and always 0.
|
|
|
|
*/
|
|
|
|
|
|
|
|
reg = ccsr_read4(OCP85XX_DDR1_CS0_CONFIG);
|
|
|
|
if (reg & (1 << 29))
|
|
|
|
tgt = OCP85XX_TGTIF_RAM_INTL;
|
|
|
|
else
|
|
|
|
tgt = OCP85XX_TGTIF_RAM1;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set BSTR to the physical address of the boot page
|
|
|
|
*/
|
|
|
|
ccsr_write4(OCP85XX_BSTRH, bptr >> 32);
|
|
|
|
ccsr_write4(OCP85XX_BSTRL, bptr);
|
|
|
|
ccsr_write4(OCP85XX_BSTAR, OCP85XX_ENA_MASK |
|
|
|
|
(tgt << OCP85XX_TRGT_SHIFT_QORIQ) | (ffsl(PAGE_SIZE) - 2));
|
|
|
|
|
|
|
|
/* Read back OCP85XX_BSTAR to synchronize write */
|
|
|
|
ccsr_read4(OCP85XX_BSTAR);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable and configure time base on new CPU.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Set TB clock source to platform clock / 32 */
|
|
|
|
reg = ccsr_read4(CCSR_CTBCKSELR);
|
|
|
|
ccsr_write4(CCSR_CTBCKSELR, reg & ~(1 << pc->pc_cpuid));
|
|
|
|
|
|
|
|
/* Enable TB */
|
|
|
|
reg = ccsr_read4(CCSR_CTBENR);
|
|
|
|
ccsr_write4(CCSR_CTBENR, reg | (1 << pc->pc_cpuid));
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Set BPTR to the physical address of the boot page
|
|
|
|
*/
|
|
|
|
bptr = (bptr >> 12) | 0x80000000u;
|
|
|
|
ccsr_write4(OCP85XX_BPTR, bptr);
|
|
|
|
__asm __volatile("isync; msync");
|
|
|
|
}
|
2013-11-11 16:14:25 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Release AP from hold-off state
|
|
|
|
*/
|
2015-12-30 03:43:25 +00:00
|
|
|
reg = ccsr_read4(brr);
|
|
|
|
ccsr_write4(brr, reg | (1 << cpuid));
|
2013-11-11 16:14:25 +00:00
|
|
|
__asm __volatile("isync; msync");
|
|
|
|
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
spin_wait:
|
2013-11-11 16:14:25 +00:00
|
|
|
timeout = 500;
|
|
|
|
while (!pc->pc_awake && timeout--)
|
|
|
|
DELAY(1000); /* wait 1ms */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable boot page translation so that the 4K page at the default
|
|
|
|
* address (= 0xfffff000) isn't permanently remapped and thus not
|
|
|
|
* usable otherwise.
|
|
|
|
*/
|
Add ePAPR boot support for PowerPC book-E (MPC85xx) hardware
Summary:
u-boot, following the ePAPR specification, puts secondary cores into a
spinloop at boot, rather than leaving them shut off. It then relies on the host
OS to write the correct values to a special spin table, located in coherent
memory (on newer implementations), or noncoherent memory (older
implementations).
This supports both implementations of ePAPR, as well as continuing to support
non-ePAPR booting, by first attempting to use the spintable, and falling back to
expecting non-started CPUs.
Test Plan:
Booted on a P5020 board. Tested before and after the changes.
Before the changes, prints the error "SMP: CPU 1 already out of hold-off state!"
and panics shortly thereafter. After the changes, same boot method lets it
complete boot.
Reviewed by: nwhitehorn
MFC after: 2 weeks
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D7494
2016-08-13 16:16:02 +00:00
|
|
|
if (!epapr_boot) {
|
|
|
|
if (mpc85xx_is_qoriq())
|
|
|
|
ccsr_write4(OCP85XX_BSTAR, 0);
|
|
|
|
else
|
|
|
|
ccsr_write4(OCP85XX_BPTR, 0);
|
|
|
|
__asm __volatile("isync; msync");
|
|
|
|
}
|
2013-11-11 16:14:25 +00:00
|
|
|
|
|
|
|
if (!pc->pc_awake)
|
2016-08-03 01:22:11 +00:00
|
|
|
panic("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid);
|
2013-11-11 16:14:25 +00:00
|
|
|
return ((pc->pc_awake) ? 0 : EBUSY);
|
|
|
|
#else
|
|
|
|
/* No SMP support */
|
|
|
|
return (ENXIO);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
mpc85xx_reset(platform_t plat)
|
|
|
|
{
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Try the dedicated reset register first.
|
|
|
|
* If the SoC doesn't have one, we'll fall
|
|
|
|
* back to using the debug control register.
|
|
|
|
*/
|
|
|
|
ccsr_write4(OCP85XX_RSTCR, 2);
|
|
|
|
|
|
|
|
/* Clear DBCR0, disables debug interrupts and events. */
|
|
|
|
mtspr(SPR_DBCR0, 0);
|
|
|
|
__asm __volatile("isync");
|
|
|
|
|
|
|
|
/* Enable Debug Interrupts in MSR. */
|
|
|
|
mtmsr(mfmsr() | PSL_DE);
|
|
|
|
|
|
|
|
/* Enable debug interrupts and issue reset. */
|
|
|
|
mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
|
|
|
|
|
|
|
|
printf("Reset failed...\n");
|
|
|
|
while (1)
|
|
|
|
;
|
|
|
|
}
|
|
|
|
|
2017-11-25 21:59:59 +00:00
|
|
|
static void
|
|
|
|
mpc85xx_smp_timebase_sync(platform_t plat, u_long tb, int ap)
|
|
|
|
{
|
|
|
|
|
|
|
|
mttb(tb);
|
|
|
|
}
|
|
|
|
|
2016-01-01 02:47:40 +00:00
|
|
|
static void
|
|
|
|
mpc85xx_idle(platform_t plat, int cpu)
|
|
|
|
{
|
|
|
|
uint32_t reg;
|
|
|
|
|
2016-08-03 01:22:11 +00:00
|
|
|
if (mpc85xx_is_qoriq()) {
|
2016-10-05 04:40:48 +00:00
|
|
|
/*
|
|
|
|
* Base binutils doesn't know what the 'wait' instruction is, so
|
|
|
|
* use the opcode encoding here.
|
|
|
|
*/
|
|
|
|
__asm __volatile("wrteei 1; .long 0x7c00007c");
|
2016-08-03 01:22:11 +00:00
|
|
|
} else {
|
|
|
|
reg = mfmsr();
|
|
|
|
/* Freescale E500 core RM section 6.4.1. */
|
|
|
|
__asm __volatile("msync; mtmsr %0; isync" ::
|
|
|
|
"r" (reg | PSL_WE));
|
|
|
|
}
|
2016-01-01 02:47:40 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mpc85xx_idle_wakeup(platform_t plat, int cpu)
|
|
|
|
{
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|