2008-05-19 01:12:10 +00:00
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/*-
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2017-11-27 14:52:40 +00:00
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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2008-05-19 01:12:10 +00:00
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* Copyright (c) 2008, Pyun YongHyeon
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_MII_ATPHYREG_H_
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#define _DEV_MII_ATPHYREG_H_
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/*
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* Registers for the Attansic/Atheros Gigabit PHY.
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*/
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/* Special Control Register */
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#define ATPHY_SCR 0x10
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#define ATPHY_SCR_JABBER_DISABLE 0x0001
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#define ATPHY_SCR_POLARITY_REVERSAL 0x0002
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#define ATPHY_SCR_SQE_TEST 0x0004
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#define ATPHY_SCR_MAC_PDOWN 0x0008
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#define ATPHY_SCR_CLK125_DISABLE 0x0010
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#define ATPHY_SCR_MDI_MANUAL_MODE 0x0000
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#define ATPHY_SCR_MDIX_MANUAL_MODE 0x0020
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#define ATPHY_SCR_AUTO_X_1000T 0x0040
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#define ATPHY_SCR_AUTO_X_MODE 0x0060
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#define ATPHY_SCR_10BT_EXT_ENABLE 0x0080
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#define ATPHY_SCR_MII_5BIT_ENABLE 0x0100
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#define ATPHY_SCR_SCRAMBLER_DISABLE 0x0200
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#define ATPHY_SCR_FORCE_LINK_GOOD 0x0400
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#define ATPHY_SCR_ASSERT_CRS_ON_TX 0x0800
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/* Special Status Register. */
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#define ATPHY_SSR 0x11
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#define ATPHY_SSR_SPD_DPLX_RESOLVED 0x0800
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#define ATPHY_SSR_DUPLEX 0x2000
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#define ATPHY_SSR_SPEED_MASK 0xC000
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#define ATPHY_SSR_10MBS 0x0000
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#define ATPHY_SSR_100MBS 0x4000
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#define ATPHY_SSR_1000MBS 0x8000
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#endif /* _DEV_MII_ATPHYREG_H_ */
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