2010-11-26 22:46:32 +00:00
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/******************************************************************************
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2017-07-05 17:27:03 +00:00
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Copyright (c) 2001-2017, Intel Corporation
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2010-11-26 22:46:32 +00:00
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All rights reserved.
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2017-07-05 17:27:03 +00:00
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Redistribution and use in source and binary forms, with or without
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2010-11-26 22:46:32 +00:00
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modification, are permitted provided that the following conditions are met:
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2017-07-05 17:27:03 +00:00
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1. Redistributions of source code must retain the above copyright notice,
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2010-11-26 22:46:32 +00:00
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this list of conditions and the following disclaimer.
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2017-07-05 17:27:03 +00:00
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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2010-11-26 22:46:32 +00:00
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documentation and/or other materials provided with the distribution.
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2017-07-05 17:27:03 +00:00
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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2010-11-26 22:46:32 +00:00
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this software without specific prior written permission.
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2017-07-05 17:27:03 +00:00
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2010-11-26 22:46:32 +00:00
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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2017-07-05 17:27:03 +00:00
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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2010-11-26 22:46:32 +00:00
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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2017-07-05 17:27:03 +00:00
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#include "ixgbe.h"
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2010-11-26 22:46:32 +00:00
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#ifndef IXGBE_VFWRITE_REG
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#define IXGBE_VFWRITE_REG IXGBE_WRITE_REG
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#endif
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#ifndef IXGBE_VFREAD_REG
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#define IXGBE_VFREAD_REG IXGBE_READ_REG
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#endif
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/**
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* ixgbe_init_ops_vf - Initialize the pointers for vf
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* @hw: pointer to hardware structure
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*
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* This will assign function pointers, adapter-specific functions can
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* override the assignment of generic function pointers by assigning
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* their own adapter-specific function pointers.
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* Does not touch the hardware.
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**/
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s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw)
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{
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/* MAC */
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hw->mac.ops.init_hw = ixgbe_init_hw_vf;
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hw->mac.ops.reset_hw = ixgbe_reset_hw_vf;
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hw->mac.ops.start_hw = ixgbe_start_hw_vf;
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/* Cannot clear stats on VF */
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hw->mac.ops.clear_hw_cntrs = NULL;
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hw->mac.ops.get_media_type = NULL;
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hw->mac.ops.get_mac_addr = ixgbe_get_mac_addr_vf;
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2012-01-30 16:42:02 +00:00
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hw->mac.ops.stop_adapter = ixgbe_stop_adapter_vf;
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2010-11-26 22:46:32 +00:00
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hw->mac.ops.get_bus_info = NULL;
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2017-07-05 17:27:03 +00:00
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hw->mac.ops.negotiate_api_version = ixgbevf_negotiate_api_version;
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2010-11-26 22:46:32 +00:00
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/* Link */
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hw->mac.ops.setup_link = ixgbe_setup_mac_link_vf;
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hw->mac.ops.check_link = ixgbe_check_mac_link_vf;
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hw->mac.ops.get_link_capabilities = NULL;
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/* RAR, Multicast, VLAN */
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hw->mac.ops.set_rar = ixgbe_set_rar_vf;
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2012-01-30 16:42:02 +00:00
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hw->mac.ops.set_uc_addr = ixgbevf_set_uc_addr_vf;
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2010-11-26 22:46:32 +00:00
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hw->mac.ops.init_rx_addrs = NULL;
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hw->mac.ops.update_mc_addr_list = ixgbe_update_mc_addr_list_vf;
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2017-07-05 17:27:03 +00:00
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hw->mac.ops.update_xcast_mode = ixgbevf_update_xcast_mode;
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2010-11-26 22:46:32 +00:00
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hw->mac.ops.enable_mc = NULL;
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hw->mac.ops.disable_mc = NULL;
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hw->mac.ops.clear_vfta = NULL;
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hw->mac.ops.set_vfta = ixgbe_set_vfta_vf;
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2017-07-05 17:27:03 +00:00
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hw->mac.ops.set_rlpml = ixgbevf_rlpml_set_vf;
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2010-11-26 22:46:32 +00:00
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hw->mac.max_tx_queues = 1;
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hw->mac.max_rx_queues = 1;
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hw->mbx.ops.init_params = ixgbe_init_mbx_params_vf;
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return IXGBE_SUCCESS;
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}
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2015-03-17 18:32:28 +00:00
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/* ixgbe_virt_clr_reg - Set register to default (power on) state.
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* @hw: pointer to hardware structure
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*/
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static void ixgbe_virt_clr_reg(struct ixgbe_hw *hw)
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{
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int i;
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u32 vfsrrctl;
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u32 vfdca_rxctrl;
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u32 vfdca_txctrl;
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/* VRSRRCTL default values (BSIZEPACKET = 2048, BSIZEHEADER = 256) */
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vfsrrctl = 0x100 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
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vfsrrctl |= 0x800 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
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/* DCA_RXCTRL default value */
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vfdca_rxctrl = IXGBE_DCA_RXCTRL_DESC_RRO_EN |
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IXGBE_DCA_RXCTRL_DATA_WRO_EN |
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IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
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/* DCA_TXCTRL default value */
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vfdca_txctrl = IXGBE_DCA_TXCTRL_DESC_RRO_EN |
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IXGBE_DCA_TXCTRL_DESC_WRO_EN |
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IXGBE_DCA_TXCTRL_DATA_RRO_EN;
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IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0);
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for (i = 0; i < 7; i++) {
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IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
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IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
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IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), 0);
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IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), vfsrrctl);
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IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
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IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
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IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), 0);
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IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAH(i), 0);
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IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAL(i), 0);
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IXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(i), vfdca_rxctrl);
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IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i), vfdca_txctrl);
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}
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IXGBE_WRITE_FLUSH(hw);
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}
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2010-11-26 22:46:32 +00:00
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/**
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* ixgbe_start_hw_vf - Prepare hardware for Tx/Rx
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* @hw: pointer to hardware structure
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*
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* Starts the hardware by filling the bus info structure and media type, clears
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* all on chip counters, initializes receive address registers, multicast
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* table, VLAN filter table, calls routine to set up link and flow control
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* settings, and leaves transmit and receive units disabled and uninitialized
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**/
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s32 ixgbe_start_hw_vf(struct ixgbe_hw *hw)
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{
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/* Clear adapter stopped flag */
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hw->adapter_stopped = FALSE;
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_init_hw_vf - virtual function hardware initialization
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* @hw: pointer to hardware structure
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*
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* Initialize the hardware by resetting the hardware and then starting
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* the hardware
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**/
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s32 ixgbe_init_hw_vf(struct ixgbe_hw *hw)
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{
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s32 status = hw->mac.ops.start_hw(hw);
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hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
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return status;
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}
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/**
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* ixgbe_reset_hw_vf - Performs hardware reset
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* @hw: pointer to hardware structure
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*
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* Resets the hardware by reseting the transmit and receive units, masks and
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* clears all interrupts.
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**/
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s32 ixgbe_reset_hw_vf(struct ixgbe_hw *hw)
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{
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struct ixgbe_mbx_info *mbx = &hw->mbx;
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u32 timeout = IXGBE_VF_INIT_TIMEOUT;
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s32 ret_val = IXGBE_ERR_INVALID_MAC_ADDR;
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2015-03-17 18:32:28 +00:00
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u32 msgbuf[IXGBE_VF_PERMADDR_MSG_LEN];
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2010-11-26 22:46:32 +00:00
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u8 *addr = (u8 *)(&msgbuf[1]);
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DEBUGFUNC("ixgbevf_reset_hw_vf");
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/* Call adapter stop to disable tx/rx and clear interrupts */
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hw->mac.ops.stop_adapter(hw);
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2015-06-01 17:43:34 +00:00
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/* reset the api version */
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hw->api_version = ixgbe_mbox_api_10;
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2013-03-04 23:07:40 +00:00
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2010-11-26 22:46:32 +00:00
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DEBUGOUT("Issuing a function level reset to MAC\n");
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2015-03-17 18:32:28 +00:00
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IXGBE_VFWRITE_REG(hw, IXGBE_VFCTRL, IXGBE_CTRL_RST);
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2012-01-30 16:42:02 +00:00
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IXGBE_WRITE_FLUSH(hw);
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msec_delay(50);
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2010-11-26 22:46:32 +00:00
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/* we cannot reset while the RSTI / RSTD bits are asserted */
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while (!mbx->ops.check_for_rst(hw, 0) && timeout) {
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timeout--;
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usec_delay(5);
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}
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2013-06-18 21:28:19 +00:00
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if (!timeout)
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return IXGBE_ERR_RESET_FAILED;
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2015-03-17 18:32:28 +00:00
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/* Reset VF registers to initial values */
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ixgbe_virt_clr_reg(hw);
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2013-06-18 21:28:19 +00:00
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/* mailbox timeout can now become active */
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mbx->timeout = IXGBE_VF_MBX_INIT_TIMEOUT;
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msgbuf[0] = IXGBE_VF_RESET;
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mbx->ops.write_posted(hw, msgbuf, 1, 0);
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msec_delay(10);
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/*
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* set our "perm_addr" based on info provided by PF
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* also set up the mc_filter_type which is piggy backed
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* on the mac address in word 3
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*/
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ret_val = mbx->ops.read_posted(hw, msgbuf,
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IXGBE_VF_PERMADDR_MSG_LEN, 0);
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if (ret_val)
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return ret_val;
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if (msgbuf[0] != (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK) &&
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msgbuf[0] != (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_NACK))
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return IXGBE_ERR_INVALID_MAC_ADDR;
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2017-07-05 17:27:03 +00:00
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if (msgbuf[0] == (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK))
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memcpy(hw->mac.perm_addr, addr, IXGBE_ETH_LENGTH_OF_ADDRESS);
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2013-06-18 21:28:19 +00:00
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hw->mac.mc_filter_type = msgbuf[IXGBE_VF_MC_TYPE_WORD];
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2010-11-26 22:46:32 +00:00
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return ret_val;
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}
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/**
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2012-01-30 16:42:02 +00:00
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* ixgbe_stop_adapter_vf - Generic stop Tx/Rx units
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2010-11-26 22:46:32 +00:00
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* @hw: pointer to hardware structure
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*
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* Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
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* disables transmit and receive units. The adapter_stopped flag is used by
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* the shared code and drivers to determine if the adapter is in a stopped
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* state and should not touch the hardware.
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**/
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2012-01-30 16:42:02 +00:00
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s32 ixgbe_stop_adapter_vf(struct ixgbe_hw *hw)
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2010-11-26 22:46:32 +00:00
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{
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u32 reg_val;
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u16 i;
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/*
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* Set the adapter_stopped flag so other driver functions stop touching
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* the hardware
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*/
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hw->adapter_stopped = TRUE;
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/* Clear interrupt mask to stop from interrupts being generated */
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IXGBE_VFWRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
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2012-01-30 16:42:02 +00:00
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/* Clear any pending interrupts, flush previous writes */
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2010-11-26 22:46:32 +00:00
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IXGBE_VFREAD_REG(hw, IXGBE_VTEICR);
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/* Disable the transmit unit. Each queue must be disabled. */
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2012-01-30 16:42:02 +00:00
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for (i = 0; i < hw->mac.max_tx_queues; i++)
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IXGBE_VFWRITE_REG(hw, IXGBE_VFTXDCTL(i), IXGBE_TXDCTL_SWFLSH);
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/* Disable the receive unit by stopping each queue */
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for (i = 0; i < hw->mac.max_rx_queues; i++) {
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reg_val = IXGBE_VFREAD_REG(hw, IXGBE_VFRXDCTL(i));
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reg_val &= ~IXGBE_RXDCTL_ENABLE;
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IXGBE_VFWRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val);
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2010-11-26 22:46:32 +00:00
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}
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2015-03-17 18:32:28 +00:00
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/* Clear packet split and pool config */
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IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0);
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2010-11-26 22:46:32 +00:00
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2012-01-30 16:42:02 +00:00
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/* flush all queues disables */
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IXGBE_WRITE_FLUSH(hw);
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msec_delay(2);
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2010-11-26 22:46:32 +00:00
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_mta_vector - Determines bit-vector in multicast table to set
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* @hw: pointer to hardware structure
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* @mc_addr: the multicast address
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*
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* Extracts the 12 bits, from a multicast address, to determine which
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* bit-vector to set in the multicast table. The hardware uses 12 bits, from
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* incoming rx multicast addresses, to determine the bit-vector to check in
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* the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
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* by the MO field of the MCSTCTRL. The MO field is set during initialization
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* to mc_filter_type.
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**/
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static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
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{
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u32 vector = 0;
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switch (hw->mac.mc_filter_type) {
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case 0: /* use bits [47:36] of the address */
|
|
|
|
vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
|
|
|
|
break;
|
|
|
|
case 1: /* use bits [46:35] of the address */
|
|
|
|
vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
|
|
|
|
break;
|
|
|
|
case 2: /* use bits [45:34] of the address */
|
|
|
|
vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
|
|
|
|
break;
|
|
|
|
case 3: /* use bits [43:32] of the address */
|
|
|
|
vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
|
|
|
|
break;
|
|
|
|
default: /* Invalid mc_filter_type */
|
|
|
|
DEBUGOUT("MC filter type param set incorrectly\n");
|
|
|
|
ASSERT(0);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* vector can only be 12-bits or boundary will be exceeded */
|
|
|
|
vector &= 0xFFF;
|
|
|
|
return vector;
|
|
|
|
}
|
|
|
|
|
2017-07-05 17:27:03 +00:00
|
|
|
static s32 ixgbevf_write_msg_read_ack(struct ixgbe_hw *hw, u32 *msg,
|
|
|
|
u32 *retmsg, u16 size)
|
2013-03-04 23:07:40 +00:00
|
|
|
{
|
|
|
|
struct ixgbe_mbx_info *mbx = &hw->mbx;
|
|
|
|
s32 retval = mbx->ops.write_posted(hw, msg, size, 0);
|
|
|
|
|
2017-07-05 17:27:03 +00:00
|
|
|
if (retval)
|
|
|
|
return retval;
|
|
|
|
|
|
|
|
return mbx->ops.read_posted(hw, retmsg, size, 0);
|
2013-03-04 23:07:40 +00:00
|
|
|
}
|
|
|
|
|
2010-11-26 22:46:32 +00:00
|
|
|
/**
|
|
|
|
* ixgbe_set_rar_vf - set device MAC address
|
|
|
|
* @hw: pointer to hardware structure
|
|
|
|
* @index: Receive address register to write
|
|
|
|
* @addr: Address to put into receive address register
|
|
|
|
* @vmdq: VMDq "set" or "pool" index
|
|
|
|
* @enable_addr: set flag that address is active
|
|
|
|
**/
|
|
|
|
s32 ixgbe_set_rar_vf(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
|
2012-01-30 16:42:02 +00:00
|
|
|
u32 enable_addr)
|
2010-11-26 22:46:32 +00:00
|
|
|
{
|
|
|
|
u32 msgbuf[3];
|
|
|
|
u8 *msg_addr = (u8 *)(&msgbuf[1]);
|
|
|
|
s32 ret_val;
|
2012-01-30 16:42:02 +00:00
|
|
|
UNREFERENCED_3PARAMETER(vmdq, enable_addr, index);
|
2010-11-26 22:46:32 +00:00
|
|
|
|
|
|
|
memset(msgbuf, 0, 12);
|
|
|
|
msgbuf[0] = IXGBE_VF_SET_MAC_ADDR;
|
|
|
|
memcpy(msg_addr, addr, 6);
|
2017-07-05 17:27:03 +00:00
|
|
|
ret_val = ixgbevf_write_msg_read_ack(hw, msgbuf, msgbuf, 3);
|
2010-11-26 22:46:32 +00:00
|
|
|
|
|
|
|
msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
|
|
|
|
|
|
|
|
/* if nacked the address was rejected, use "perm_addr" */
|
|
|
|
if (!ret_val &&
|
2017-07-05 17:27:03 +00:00
|
|
|
(msgbuf[0] == (IXGBE_VF_SET_MAC_ADDR | IXGBE_VT_MSGTYPE_NACK))) {
|
2010-11-26 22:46:32 +00:00
|
|
|
ixgbe_get_mac_addr_vf(hw, hw->mac.addr);
|
2017-07-05 17:27:03 +00:00
|
|
|
return IXGBE_ERR_MBX;
|
|
|
|
}
|
2010-11-26 22:46:32 +00:00
|
|
|
|
|
|
|
return ret_val;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* ixgbe_update_mc_addr_list_vf - Update Multicast addresses
|
|
|
|
* @hw: pointer to the HW structure
|
|
|
|
* @mc_addr_list: array of multicast addresses to program
|
|
|
|
* @mc_addr_count: number of multicast addresses to program
|
|
|
|
* @next: caller supplied function to return next address in list
|
|
|
|
*
|
|
|
|
* Updates the Multicast Table Array.
|
|
|
|
**/
|
|
|
|
s32 ixgbe_update_mc_addr_list_vf(struct ixgbe_hw *hw, u8 *mc_addr_list,
|
2012-01-30 16:42:02 +00:00
|
|
|
u32 mc_addr_count, ixgbe_mc_addr_itr next,
|
|
|
|
bool clear)
|
2010-11-26 22:46:32 +00:00
|
|
|
{
|
|
|
|
struct ixgbe_mbx_info *mbx = &hw->mbx;
|
|
|
|
u32 msgbuf[IXGBE_VFMAILBOX_SIZE];
|
|
|
|
u16 *vector_list = (u16 *)&msgbuf[1];
|
|
|
|
u32 vector;
|
|
|
|
u32 cnt, i;
|
|
|
|
u32 vmdq;
|
|
|
|
|
2012-01-30 16:42:02 +00:00
|
|
|
UNREFERENCED_1PARAMETER(clear);
|
|
|
|
|
2010-11-26 22:46:32 +00:00
|
|
|
DEBUGFUNC("ixgbe_update_mc_addr_list_vf");
|
|
|
|
|
|
|
|
/* Each entry in the list uses 1 16 bit word. We have 30
|
|
|
|
* 16 bit words available in our HW msg buffer (minus 1 for the
|
|
|
|
* msg type). That's 30 hash values if we pack 'em right. If
|
|
|
|
* there are more than 30 MC addresses to add then punt the
|
|
|
|
* extras for now and then add code to handle more than 30 later.
|
|
|
|
* It would be unusual for a server to request that many multi-cast
|
|
|
|
* addresses except for in large enterprise network environments.
|
|
|
|
*/
|
|
|
|
|
|
|
|
DEBUGOUT1("MC Addr Count = %d\n", mc_addr_count);
|
|
|
|
|
|
|
|
cnt = (mc_addr_count > 30) ? 30 : mc_addr_count;
|
|
|
|
msgbuf[0] = IXGBE_VF_SET_MULTICAST;
|
|
|
|
msgbuf[0] |= cnt << IXGBE_VT_MSGINFO_SHIFT;
|
|
|
|
|
|
|
|
for (i = 0; i < cnt; i++) {
|
|
|
|
vector = ixgbe_mta_vector(hw, next(hw, &mc_addr_list, &vmdq));
|
|
|
|
DEBUGOUT1("Hash value = 0x%03X\n", vector);
|
|
|
|
vector_list[i] = (u16)vector;
|
|
|
|
}
|
|
|
|
|
|
|
|
return mbx->ops.write_posted(hw, msgbuf, IXGBE_VFMAILBOX_SIZE, 0);
|
|
|
|
}
|
|
|
|
|
2017-07-05 17:27:03 +00:00
|
|
|
/**
|
|
|
|
* ixgbevf_update_xcast_mode - Update Multicast mode
|
|
|
|
* @hw: pointer to the HW structure
|
|
|
|
* @xcast_mode: new multicast mode
|
|
|
|
*
|
|
|
|
* Updates the Multicast Mode of VF.
|
|
|
|
**/
|
|
|
|
s32 ixgbevf_update_xcast_mode(struct ixgbe_hw *hw, int xcast_mode)
|
|
|
|
{
|
|
|
|
u32 msgbuf[2];
|
|
|
|
s32 err;
|
|
|
|
|
|
|
|
switch (hw->api_version) {
|
|
|
|
case ixgbe_mbox_api_12:
|
|
|
|
/* New modes were introduced in 1.3 version */
|
|
|
|
if (xcast_mode > IXGBEVF_XCAST_MODE_ALLMULTI)
|
|
|
|
return IXGBE_ERR_FEATURE_NOT_SUPPORTED;
|
|
|
|
/* Fall through */
|
|
|
|
case ixgbe_mbox_api_13:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return IXGBE_ERR_FEATURE_NOT_SUPPORTED;
|
|
|
|
}
|
|
|
|
|
|
|
|
msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
|
|
|
|
msgbuf[1] = xcast_mode;
|
|
|
|
|
|
|
|
err = ixgbevf_write_msg_read_ack(hw, msgbuf, msgbuf, 2);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
|
|
|
|
if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
|
|
|
|
return IXGBE_ERR_FEATURE_NOT_SUPPORTED;
|
|
|
|
return IXGBE_SUCCESS;
|
|
|
|
}
|
|
|
|
|
2010-11-26 22:46:32 +00:00
|
|
|
/**
|
|
|
|
* ixgbe_set_vfta_vf - Set/Unset vlan filter table address
|
|
|
|
* @hw: pointer to the HW structure
|
|
|
|
* @vlan: 12 bit VLAN ID
|
|
|
|
* @vind: unused by VF drivers
|
|
|
|
* @vlan_on: if TRUE then set bit, else clear bit
|
2017-07-05 17:27:03 +00:00
|
|
|
* @vlvf_bypass: boolean flag indicating updating default pool is okay
|
|
|
|
*
|
|
|
|
* Turn on/off specified VLAN in the VLAN filter table.
|
2010-11-26 22:46:32 +00:00
|
|
|
**/
|
2017-07-05 17:27:03 +00:00
|
|
|
s32 ixgbe_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind,
|
|
|
|
bool vlan_on, bool vlvf_bypass)
|
2010-11-26 22:46:32 +00:00
|
|
|
{
|
|
|
|
u32 msgbuf[2];
|
2012-07-05 20:51:44 +00:00
|
|
|
s32 ret_val;
|
2017-07-05 17:27:03 +00:00
|
|
|
UNREFERENCED_2PARAMETER(vind, vlvf_bypass);
|
2010-11-26 22:46:32 +00:00
|
|
|
|
|
|
|
msgbuf[0] = IXGBE_VF_SET_VLAN;
|
|
|
|
msgbuf[1] = vlan;
|
|
|
|
/* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
|
|
|
|
msgbuf[0] |= vlan_on << IXGBE_VT_MSGINFO_SHIFT;
|
|
|
|
|
2017-07-05 17:27:03 +00:00
|
|
|
ret_val = ixgbevf_write_msg_read_ack(hw, msgbuf, msgbuf, 2);
|
2012-07-05 20:51:44 +00:00
|
|
|
if (!ret_val && (msgbuf[0] & IXGBE_VT_MSGTYPE_ACK))
|
|
|
|
return IXGBE_SUCCESS;
|
|
|
|
|
|
|
|
return ret_val | (msgbuf[0] & IXGBE_VT_MSGTYPE_NACK);
|
2010-11-26 22:46:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* ixgbe_get_num_of_tx_queues_vf - Get number of TX queues
|
|
|
|
* @hw: pointer to hardware structure
|
|
|
|
*
|
|
|
|
* Returns the number of transmit queues for the given adapter.
|
|
|
|
**/
|
|
|
|
u32 ixgbe_get_num_of_tx_queues_vf(struct ixgbe_hw *hw)
|
|
|
|
{
|
2012-01-30 16:42:02 +00:00
|
|
|
UNREFERENCED_1PARAMETER(hw);
|
2010-11-26 22:46:32 +00:00
|
|
|
return IXGBE_VF_MAX_TX_QUEUES;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* ixgbe_get_num_of_rx_queues_vf - Get number of RX queues
|
|
|
|
* @hw: pointer to hardware structure
|
|
|
|
*
|
|
|
|
* Returns the number of receive queues for the given adapter.
|
|
|
|
**/
|
|
|
|
u32 ixgbe_get_num_of_rx_queues_vf(struct ixgbe_hw *hw)
|
|
|
|
{
|
2012-01-30 16:42:02 +00:00
|
|
|
UNREFERENCED_1PARAMETER(hw);
|
2010-11-26 22:46:32 +00:00
|
|
|
return IXGBE_VF_MAX_RX_QUEUES;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* ixgbe_get_mac_addr_vf - Read device MAC address
|
|
|
|
* @hw: pointer to the HW structure
|
|
|
|
**/
|
|
|
|
s32 ixgbe_get_mac_addr_vf(struct ixgbe_hw *hw, u8 *mac_addr)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < IXGBE_ETH_LENGTH_OF_ADDRESS; i++)
|
|
|
|
mac_addr[i] = hw->mac.perm_addr[i];
|
|
|
|
|
|
|
|
return IXGBE_SUCCESS;
|
|
|
|
}
|
|
|
|
|
2012-01-30 16:42:02 +00:00
|
|
|
s32 ixgbevf_set_uc_addr_vf(struct ixgbe_hw *hw, u32 index, u8 *addr)
|
|
|
|
{
|
2017-07-05 17:27:03 +00:00
|
|
|
u32 msgbuf[3], msgbuf_chk;
|
2012-01-30 16:42:02 +00:00
|
|
|
u8 *msg_addr = (u8 *)(&msgbuf[1]);
|
|
|
|
s32 ret_val;
|
|
|
|
|
|
|
|
memset(msgbuf, 0, sizeof(msgbuf));
|
|
|
|
/*
|
|
|
|
* If index is one then this is the start of a new list and needs
|
|
|
|
* indication to the PF so it can do it's own list management.
|
|
|
|
* If it is zero then that tells the PF to just clear all of
|
|
|
|
* this VF's macvlans and there is no new list.
|
|
|
|
*/
|
|
|
|
msgbuf[0] |= index << IXGBE_VT_MSGINFO_SHIFT;
|
|
|
|
msgbuf[0] |= IXGBE_VF_SET_MACVLAN;
|
2017-07-05 17:27:03 +00:00
|
|
|
msgbuf_chk = msgbuf[0];
|
2012-01-30 16:42:02 +00:00
|
|
|
if (addr)
|
|
|
|
memcpy(msg_addr, addr, 6);
|
|
|
|
|
2017-07-05 17:27:03 +00:00
|
|
|
ret_val = ixgbevf_write_msg_read_ack(hw, msgbuf, msgbuf, 3);
|
|
|
|
if (!ret_val) {
|
|
|
|
msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
|
2012-01-30 16:42:02 +00:00
|
|
|
|
2017-07-05 17:27:03 +00:00
|
|
|
if (msgbuf[0] == (msgbuf_chk | IXGBE_VT_MSGTYPE_NACK))
|
|
|
|
return IXGBE_ERR_OUT_OF_MEM;
|
|
|
|
}
|
2012-01-30 16:42:02 +00:00
|
|
|
|
|
|
|
return ret_val;
|
|
|
|
}
|
|
|
|
|
2010-11-26 22:46:32 +00:00
|
|
|
/**
|
|
|
|
* ixgbe_setup_mac_link_vf - Setup MAC link settings
|
|
|
|
* @hw: pointer to hardware structure
|
|
|
|
* @speed: new link speed
|
|
|
|
* @autoneg: TRUE if autonegotiation enabled
|
|
|
|
* @autoneg_wait_to_complete: TRUE when waiting for completion is needed
|
|
|
|
*
|
|
|
|
* Set the link speed in the AUTOC register and restarts link.
|
|
|
|
**/
|
2013-03-04 23:07:40 +00:00
|
|
|
s32 ixgbe_setup_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed speed,
|
2012-01-30 16:42:02 +00:00
|
|
|
bool autoneg_wait_to_complete)
|
2010-11-26 22:46:32 +00:00
|
|
|
{
|
2013-03-04 23:07:40 +00:00
|
|
|
UNREFERENCED_3PARAMETER(hw, speed, autoneg_wait_to_complete);
|
2010-11-26 22:46:32 +00:00
|
|
|
return IXGBE_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* ixgbe_check_mac_link_vf - Get link/speed status
|
|
|
|
* @hw: pointer to hardware structure
|
|
|
|
* @speed: pointer to link speed
|
|
|
|
* @link_up: TRUE is link is up, FALSE otherwise
|
|
|
|
* @autoneg_wait_to_complete: TRUE when waiting for completion is needed
|
|
|
|
*
|
|
|
|
* Reads the links register to determine if link is up and the current speed
|
|
|
|
**/
|
|
|
|
s32 ixgbe_check_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
|
2012-01-30 16:42:02 +00:00
|
|
|
bool *link_up, bool autoneg_wait_to_complete)
|
2010-11-26 22:46:32 +00:00
|
|
|
{
|
2013-03-04 23:07:40 +00:00
|
|
|
struct ixgbe_mbx_info *mbx = &hw->mbx;
|
|
|
|
struct ixgbe_mac_info *mac = &hw->mac;
|
|
|
|
s32 ret_val = IXGBE_SUCCESS;
|
2010-11-26 22:46:32 +00:00
|
|
|
u32 links_reg;
|
2013-03-04 23:07:40 +00:00
|
|
|
u32 in_msg = 0;
|
2012-01-30 16:42:02 +00:00
|
|
|
UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
|
2010-11-26 22:46:32 +00:00
|
|
|
|
2013-03-04 23:07:40 +00:00
|
|
|
/* If we were hit with a reset drop the link */
|
|
|
|
if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
|
|
|
|
mac->get_link_status = TRUE;
|
2010-11-26 22:46:32 +00:00
|
|
|
|
2013-03-04 23:07:40 +00:00
|
|
|
if (!mac->get_link_status)
|
|
|
|
goto out;
|
2010-11-26 22:46:32 +00:00
|
|
|
|
2013-03-04 23:07:40 +00:00
|
|
|
/* if link status is down no point in checking to see if pf is up */
|
|
|
|
links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
|
|
|
|
if (!(links_reg & IXGBE_LINKS_UP))
|
|
|
|
goto out;
|
2010-11-26 22:46:32 +00:00
|
|
|
|
2015-03-17 18:32:28 +00:00
|
|
|
/* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
|
|
|
|
* before the link status is correct
|
|
|
|
*/
|
|
|
|
if (mac->type == ixgbe_mac_82599_vf) {
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 5; i++) {
|
|
|
|
usec_delay(100);
|
|
|
|
links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
|
|
|
|
|
|
|
|
if (!(links_reg & IXGBE_LINKS_UP))
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-03-04 23:07:40 +00:00
|
|
|
switch (links_reg & IXGBE_LINKS_SPEED_82599) {
|
2012-07-05 20:51:44 +00:00
|
|
|
case IXGBE_LINKS_SPEED_10G_82599:
|
2010-11-26 22:46:32 +00:00
|
|
|
*speed = IXGBE_LINK_SPEED_10GB_FULL;
|
2017-07-05 17:27:03 +00:00
|
|
|
if (hw->mac.type >= ixgbe_mac_X550) {
|
|
|
|
if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
|
|
|
|
*speed = IXGBE_LINK_SPEED_2_5GB_FULL;
|
|
|
|
}
|
2012-07-05 20:51:44 +00:00
|
|
|
break;
|
|
|
|
case IXGBE_LINKS_SPEED_1G_82599:
|
2010-11-26 22:46:32 +00:00
|
|
|
*speed = IXGBE_LINK_SPEED_1GB_FULL;
|
2012-07-05 20:51:44 +00:00
|
|
|
break;
|
|
|
|
case IXGBE_LINKS_SPEED_100_82599:
|
|
|
|
*speed = IXGBE_LINK_SPEED_100_FULL;
|
2017-07-05 17:27:03 +00:00
|
|
|
if (hw->mac.type == ixgbe_mac_X550) {
|
|
|
|
if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
|
|
|
|
*speed = IXGBE_LINK_SPEED_5GB_FULL;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case IXGBE_LINKS_SPEED_10_X550EM_A:
|
|
|
|
*speed = IXGBE_LINK_SPEED_UNKNOWN;
|
|
|
|
/* Since Reserved in older MAC's */
|
|
|
|
if (hw->mac.type >= ixgbe_mac_X550)
|
|
|
|
*speed = IXGBE_LINK_SPEED_10_FULL;
|
2012-07-05 20:51:44 +00:00
|
|
|
break;
|
2017-07-05 17:27:03 +00:00
|
|
|
default:
|
|
|
|
*speed = IXGBE_LINK_SPEED_UNKNOWN;
|
2012-07-05 20:51:44 +00:00
|
|
|
}
|
2010-11-26 22:46:32 +00:00
|
|
|
|
2013-03-04 23:07:40 +00:00
|
|
|
/* if the read failed it could just be a mailbox collision, best wait
|
|
|
|
* until we are called again and don't report an error
|
|
|
|
*/
|
|
|
|
if (mbx->ops.read(hw, &in_msg, 1, 0))
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
|
|
|
|
/* msg is not CTS and is NACK we must have lost CTS status */
|
|
|
|
if (in_msg & IXGBE_VT_MSGTYPE_NACK)
|
|
|
|
ret_val = -1;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* the pf is talking, if we timed out in the past we reinit */
|
|
|
|
if (!mbx->timeout) {
|
|
|
|
ret_val = -1;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* if we passed all the tests above then the link is up and we no
|
|
|
|
* longer need to check for link
|
|
|
|
*/
|
|
|
|
mac->get_link_status = FALSE;
|
|
|
|
|
|
|
|
out:
|
|
|
|
*link_up = !mac->get_link_status;
|
|
|
|
return ret_val;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* ixgbevf_rlpml_set_vf - Set the maximum receive packet length
|
|
|
|
* @hw: pointer to the HW structure
|
|
|
|
* @max_size: value to assign to max frame size
|
|
|
|
**/
|
2017-07-05 17:27:03 +00:00
|
|
|
s32 ixgbevf_rlpml_set_vf(struct ixgbe_hw *hw, u16 max_size)
|
2013-03-04 23:07:40 +00:00
|
|
|
{
|
|
|
|
u32 msgbuf[2];
|
2017-07-05 17:27:03 +00:00
|
|
|
s32 retval;
|
2013-03-04 23:07:40 +00:00
|
|
|
|
|
|
|
msgbuf[0] = IXGBE_VF_SET_LPE;
|
|
|
|
msgbuf[1] = max_size;
|
2017-07-05 17:27:03 +00:00
|
|
|
|
|
|
|
retval = ixgbevf_write_msg_read_ack(hw, msgbuf, msgbuf, 2);
|
|
|
|
if (retval)
|
|
|
|
return retval;
|
|
|
|
if ((msgbuf[0] & IXGBE_VF_SET_LPE) &&
|
|
|
|
(msgbuf[0] & IXGBE_VT_MSGTYPE_NACK))
|
|
|
|
return IXGBE_ERR_MBX;
|
|
|
|
|
|
|
|
return 0;
|
2013-03-04 23:07:40 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* ixgbevf_negotiate_api_version - Negotiate supported API version
|
|
|
|
* @hw: pointer to the HW structure
|
|
|
|
* @api: integer containing requested API version
|
|
|
|
**/
|
|
|
|
int ixgbevf_negotiate_api_version(struct ixgbe_hw *hw, int api)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
u32 msg[3];
|
|
|
|
|
|
|
|
/* Negotiate the mailbox API version */
|
|
|
|
msg[0] = IXGBE_VF_API_NEGOTIATE;
|
|
|
|
msg[1] = api;
|
|
|
|
msg[2] = 0;
|
|
|
|
|
2017-07-05 17:27:03 +00:00
|
|
|
err = ixgbevf_write_msg_read_ack(hw, msg, msg, 3);
|
2013-03-04 23:07:40 +00:00
|
|
|
if (!err) {
|
|
|
|
msg[0] &= ~IXGBE_VT_MSGTYPE_CTS;
|
|
|
|
|
|
|
|
/* Store value and return 0 on success */
|
|
|
|
if (msg[0] == (IXGBE_VF_API_NEGOTIATE | IXGBE_VT_MSGTYPE_ACK)) {
|
|
|
|
hw->api_version = api;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = IXGBE_ERR_INVALID_ARGUMENT;
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
int ixgbevf_get_queues(struct ixgbe_hw *hw, unsigned int *num_tcs,
|
|
|
|
unsigned int *default_tc)
|
|
|
|
{
|
2015-06-01 17:43:34 +00:00
|
|
|
int err;
|
|
|
|
u32 msg[5];
|
|
|
|
|
|
|
|
/* do nothing if API doesn't support ixgbevf_get_queues */
|
|
|
|
switch (hw->api_version) {
|
|
|
|
case ixgbe_mbox_api_11:
|
2017-07-05 17:27:03 +00:00
|
|
|
case ixgbe_mbox_api_12:
|
|
|
|
case ixgbe_mbox_api_13:
|
2015-06-01 17:43:34 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Fetch queue configuration from the PF */
|
|
|
|
msg[0] = IXGBE_VF_GET_QUEUES;
|
|
|
|
msg[1] = msg[2] = msg[3] = msg[4] = 0;
|
|
|
|
|
2017-07-05 17:27:03 +00:00
|
|
|
err = ixgbevf_write_msg_read_ack(hw, msg, msg, 5);
|
2015-06-01 17:43:34 +00:00
|
|
|
if (!err) {
|
|
|
|
msg[0] &= ~IXGBE_VT_MSGTYPE_CTS;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* if we we didn't get an ACK there must have been
|
|
|
|
* some sort of mailbox error so we should treat it
|
|
|
|
* as such
|
|
|
|
*/
|
|
|
|
if (msg[0] != (IXGBE_VF_GET_QUEUES | IXGBE_VT_MSGTYPE_ACK))
|
|
|
|
return IXGBE_ERR_MBX;
|
|
|
|
|
|
|
|
/* record and validate values from message */
|
|
|
|
hw->mac.max_tx_queues = msg[IXGBE_VF_TX_QUEUES];
|
|
|
|
if (hw->mac.max_tx_queues == 0 ||
|
|
|
|
hw->mac.max_tx_queues > IXGBE_VF_MAX_TX_QUEUES)
|
|
|
|
hw->mac.max_tx_queues = IXGBE_VF_MAX_TX_QUEUES;
|
|
|
|
|
|
|
|
hw->mac.max_rx_queues = msg[IXGBE_VF_RX_QUEUES];
|
|
|
|
if (hw->mac.max_rx_queues == 0 ||
|
|
|
|
hw->mac.max_rx_queues > IXGBE_VF_MAX_RX_QUEUES)
|
|
|
|
hw->mac.max_rx_queues = IXGBE_VF_MAX_RX_QUEUES;
|
|
|
|
|
|
|
|
*num_tcs = msg[IXGBE_VF_TRANS_VLAN];
|
|
|
|
/* in case of unknown state assume we cannot tag frames */
|
|
|
|
if (*num_tcs > hw->mac.max_rx_queues)
|
|
|
|
*num_tcs = 1;
|
|
|
|
|
|
|
|
*default_tc = msg[IXGBE_VF_DEF_QUEUE];
|
|
|
|
/* default to queue 0 on out-of-bounds queue number */
|
|
|
|
if (*default_tc >= hw->mac.max_tx_queues)
|
|
|
|
*default_tc = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
2010-11-26 22:46:32 +00:00
|
|
|
}
|