2008-05-16 18:46:30 +00:00
|
|
|
/******************************************************************************
|
2007-07-11 23:03:16 +00:00
|
|
|
|
2008-05-16 18:46:30 +00:00
|
|
|
Copyright (c) 2001-2008, Intel Corporation
|
2007-07-11 23:03:16 +00:00
|
|
|
All rights reserved.
|
|
|
|
|
|
|
|
Redistribution and use in source and binary forms, with or without
|
|
|
|
modification, are permitted provided that the following conditions are met:
|
|
|
|
|
|
|
|
1. Redistributions of source code must retain the above copyright notice,
|
|
|
|
this list of conditions and the following disclaimer.
|
|
|
|
|
|
|
|
2. Redistributions in binary form must reproduce the above copyright
|
|
|
|
notice, this list of conditions and the following disclaimer in the
|
|
|
|
documentation and/or other materials provided with the distribution.
|
|
|
|
|
|
|
|
3. Neither the name of the Intel Corporation nor the names of its
|
|
|
|
contributors may be used to endorse or promote products derived from
|
|
|
|
this software without specific prior written permission.
|
|
|
|
|
|
|
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
|
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
|
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
|
|
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
|
|
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
|
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
|
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
|
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
|
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
|
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
|
|
POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
|
2008-05-16 18:46:30 +00:00
|
|
|
******************************************************************************/
|
|
|
|
/*$FreeBSD$*/
|
2007-07-11 23:03:16 +00:00
|
|
|
|
|
|
|
#ifndef _IXGBE_PHY_H_
|
|
|
|
#define _IXGBE_PHY_H_
|
|
|
|
|
|
|
|
#include "ixgbe_type.h"
|
2008-11-26 23:41:18 +00:00
|
|
|
#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0
|
|
|
|
|
|
|
|
/* EEPROM byte offsets */
|
|
|
|
#define IXGBE_SFF_IDENTIFIER 0x0
|
|
|
|
#define IXGBE_SFF_IDENTIFIER_SFP 0x3
|
|
|
|
#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25
|
|
|
|
#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26
|
|
|
|
#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27
|
|
|
|
#define IXGBE_SFF_1GBE_COMP_CODES 0x6
|
|
|
|
#define IXGBE_SFF_10GBE_COMP_CODES 0x3
|
|
|
|
#define IXGBE_SFF_TRANSMISSION_MEDIA 0x9
|
|
|
|
|
|
|
|
/* Bitmasks */
|
|
|
|
#define IXGBE_SFF_TWIN_AX_CAPABLE 0x80
|
|
|
|
#define IXGBE_SFF_1GBASESX_CAPABLE 0x1
|
|
|
|
#define IXGBE_SFF_10GBASESR_CAPABLE 0x10
|
|
|
|
#define IXGBE_SFF_10GBASELR_CAPABLE 0x20
|
|
|
|
#define IXGBE_I2C_EEPROM_READ_MASK 0x100
|
|
|
|
#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
|
|
|
|
#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
|
|
|
|
#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1
|
|
|
|
#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
|
|
|
|
#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
|
|
|
|
|
|
|
|
/* Bit-shift macros */
|
|
|
|
#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 12
|
|
|
|
#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 8
|
|
|
|
#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 4
|
|
|
|
|
|
|
|
/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
|
|
|
|
#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
|
|
|
|
#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
|
|
|
|
#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
|
|
|
|
|
|
|
|
/* I2C SDA and SCL timing parameters for standard mode */
|
|
|
|
#define IXGBE_I2C_T_HD_STA 4
|
|
|
|
#define IXGBE_I2C_T_LOW 5
|
|
|
|
#define IXGBE_I2C_T_HIGH 4
|
|
|
|
#define IXGBE_I2C_T_SU_STA 5
|
|
|
|
#define IXGBE_I2C_T_HD_DATA 5
|
|
|
|
#define IXGBE_I2C_T_SU_DATA 1
|
|
|
|
#define IXGBE_I2C_T_RISE 1
|
|
|
|
#define IXGBE_I2C_T_FALL 1
|
|
|
|
#define IXGBE_I2C_T_SU_STO 4
|
|
|
|
#define IXGBE_I2C_T_BUF 5
|
|
|
|
|
2007-07-11 23:03:16 +00:00
|
|
|
|
2008-05-16 18:46:30 +00:00
|
|
|
s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
|
2007-07-11 23:03:16 +00:00
|
|
|
bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
|
|
|
|
enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
|
|
|
|
s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
|
|
|
|
s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
|
|
|
|
s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
|
|
|
|
s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
|
2008-05-16 18:46:30 +00:00
|
|
|
u32 device_type, u16 *phy_data);
|
2007-07-11 23:03:16 +00:00
|
|
|
s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
|
2008-05-16 18:46:30 +00:00
|
|
|
u32 device_type, u16 phy_data);
|
|
|
|
s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
|
|
|
|
s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
|
|
|
|
ixgbe_link_speed speed,
|
|
|
|
bool autoneg,
|
|
|
|
bool autoneg_wait_to_complete);
|
2007-07-11 23:03:16 +00:00
|
|
|
|
2008-05-16 18:46:30 +00:00
|
|
|
/* PHY specific */
|
|
|
|
s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
|
|
|
|
ixgbe_link_speed *speed,
|
|
|
|
bool *link_up);
|
|
|
|
s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
|
|
|
|
u16 *firmware_version);
|
|
|
|
|
2008-11-26 23:41:18 +00:00
|
|
|
s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
|
|
|
|
s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
|
|
|
|
s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
|
|
|
|
u16 *list_offset,
|
|
|
|
u16 *data_offset);
|
2007-07-11 23:03:16 +00:00
|
|
|
#endif /* _IXGBE_PHY_H_ */
|