o Implement shared pagetables and switch from 4 to 3 levels page
memory system. RISC-V ISA has only single page table base register for both kernel and user addresses translation. Before this commit we were using an extra (4th) level of pagetables for switching between kernel and user pagetables, but then realized FPGA hardware has 3-level page system hardcoded. It is also become clear that the bitfile synthesized for 4-level system is untested/broken, so we can't use extra level for switching. We are now share level 1 of pagetables between kernel and user VA. This requires to keep track of all the user pmaps created and once we adding L1 page to kernel pmap we have to add it to all the user pmaps. o Change the VM layout as we must have topmost bit to be 1 in the selected page system for kernel addresses and 0 for user addresses. o Implement pmap_kenter_device(). o Create the l3 tables for the early devmap. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
This commit is contained in:
Ruslan Bukin
parent
21e2c118b8
commit
02a371289a
@ -46,9 +46,8 @@
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#define PCPU_MD_FIELDS \
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uint32_t pc_pending_ipis; /* IPIs pending to this CPU */ \
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uint64_t pc_sptbr; /* L0 page table base (VA) */ \
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uint64_t pc_reg; /* CPU MMIO base (PA) */ \
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char __pad[109]
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char __pad[117]
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#ifdef _KERNEL
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@ -74,12 +74,18 @@ struct pv_addr {
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vm_paddr_t pv_pa;
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};
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/* An entry in the list of all pmaps */
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struct pmap_list_entry {
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SLIST_ENTRY(pmap_list_entry) pmap_link;
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struct pmap *pmap;
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};
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struct pmap {
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struct mtx pm_mtx;
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struct pmap_statistics pm_stats; /* pmap statictics */
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pd_entry_t *pm_l1;
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TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */
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struct pmap_list_entry *p_entry; /* Place in the list of all pmaps */
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};
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typedef struct pv_entry {
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@ -153,12 +153,12 @@
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#define VM_MAX_ADDRESS (0xffffffffffffffffUL)
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/* 32 GiB of kernel addresses */
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#define VM_MIN_KERNEL_ADDRESS (0xffffff8000000000UL)
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#define VM_MAX_KERNEL_ADDRESS (0xffffff8800000000UL)
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#define VM_MIN_KERNEL_ADDRESS (0xffffffc000000000UL)
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#define VM_MAX_KERNEL_ADDRESS (0xffffffc800000000UL)
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/* Direct Map for 128 GiB of PA: 0x0 - 0x1fffffffff */
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#define DMAP_MIN_ADDRESS (0xffffffc000000000UL)
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#define DMAP_MAX_ADDRESS (0xffffffdfffffffffUL)
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#define DMAP_MIN_ADDRESS (0xffffffd000000000UL)
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#define DMAP_MAX_ADDRESS (0xffffffefffffffffUL)
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#define DMAP_MIN_PHYSADDR (0x0000000000000000UL)
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#define DMAP_MAX_PHYSADDR (DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)
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@ -187,7 +187,7 @@
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})
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#define VM_MIN_USER_ADDRESS (0x0000000000000000UL)
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#define VM_MAX_USER_ADDRESS (0x0000008000000000UL)
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#define VM_MAX_USER_ADDRESS (0x0000004000000000UL)
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#define VM_MINUSER_ADDRESS (VM_MIN_USER_ADDRESS)
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#define VM_MAXUSER_ADDRESS (VM_MAX_USER_ADDRESS)
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@ -58,6 +58,7 @@ __FBSDID("$FreeBSD$");
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ASSYM(KERNBASE, KERNBASE);
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ASSYM(VM_MAXUSER_ADDRESS, VM_MAXUSER_ADDRESS);
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ASSYM(VM_MAX_KERNEL_ADDRESS, VM_MAX_KERNEL_ADDRESS);
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ASSYM(TDF_ASTPENDING, TDF_ASTPENDING);
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ASSYM(TDF_NEEDRESCHED, TDF_NEEDRESCHED);
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@ -75,7 +76,6 @@ ASSYM(PCB_A, offsetof(struct pcb, pcb_a));
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ASSYM(SF_UC, offsetof(struct sigframe, sf_uc));
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ASSYM(PC_CURPCB, offsetof(struct pcpu, pc_curpcb));
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ASSYM(PC_SPTBR, offsetof(struct pcpu, pc_sptbr));
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ASSYM(PC_CURTHREAD, offsetof(struct pcpu, pc_curthread));
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ASSYM(TD_PCB, offsetof(struct thread, td_pcb));
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@ -141,36 +141,31 @@ _start:
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/* Page tables */
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/* Level 0 */
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la s1, pagetable_l0
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la s2, pagetable_l1 /* Link to next level PN */
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/* Create an L1 page for early devmap */
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la s1, pagetable_l1
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la s2, pagetable_l2_devmap /* Link to next level PN */
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srli s2, s2, PAGE_SHIFT
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li a5, (VM_MAX_KERNEL_ADDRESS - L2_SIZE)
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srli a5, a5, L1_SHIFT /* >> L1_SHIFT */
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andi a5, a5, 0x1ff /* & 0x1ff */
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li t4, (PTE_VALID | (PTE_TYPE_PTR << PTE_TYPE_S))
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slli t5, s2, PTE_PPN0_S /* (s2 << PTE_PPN0_S) */
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or t6, t4, t5
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/* Store single level0 PTE entry to position */
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li a5, 0x1ff
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/* Store single level1 PTE entry to position */
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li a6, PTE_SIZE
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mulw a5, a5, a6
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add t0, s1, a5
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/* Store it to pagetable_l0 for each cpu */
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li t1, MAXCPU
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li t2, PAGE_SIZE
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1:
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sd t6, 0(t0)
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add t0, t0, t2
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addi t1, t1, -1
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bnez t1, 1b
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sd t6, (t0)
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/* Level 1 */
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/* Add single Level 1 entry for kernel */
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la s1, pagetable_l1
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la s2, pagetable_l2 /* Link to next level PN */
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srli s2, s2, PAGE_SHIFT
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li a5, KERNBASE
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srli a5, a5, 0x1e /* >> 30 */
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srli a5, a5, L1_SHIFT /* >> L1_SHIFT */
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andi a5, a5, 0x1ff /* & 0x1ff */
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li t4, (PTE_VALID | (PTE_TYPE_PTR << PTE_TYPE_S))
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slli t5, s2, PTE_PPN0_S /* (s2 << PTE_PPN0_S) */
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@ -198,13 +193,13 @@ _start:
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bltu t4, t3, 2b
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/* Set page tables base register */
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la s1, pagetable_l0
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la s1, pagetable_l1
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csrw sptbr, s1
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/* Page tables END */
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/* Enter supervisor mode */
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li s0, ((MSTATUS_VM_SV48 << MSTATUS_VM_SHIFT) | \
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li s0, ((MSTATUS_VM_SV39 << MSTATUS_VM_SHIFT) | \
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(MSTATUS_PRV_M << MSTATUS_PRV_SHIFT) | \
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(MSTATUS_PRV_S << MSTATUS_PRV1_SHIFT) | \
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(MSTATUS_PRV_U << MSTATUS_PRV2_SHIFT));
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@ -290,14 +285,12 @@ szsigcode:
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.quad esigcode - sigcode
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.align 12
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.globl pagetable_l0
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pagetable_l0:
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.space (PAGE_SIZE * MAXCPU)
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pagetable_l1:
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.space PAGE_SIZE
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pagetable_l2:
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.space PAGE_SIZE
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pagetable_end:
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pagetable_l2_devmap:
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.space PAGE_SIZE
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.globl init_pt_va
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init_pt_va:
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@ -336,15 +329,11 @@ ENTRY(mpentry)
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build_ring
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/* Set page tables base register */
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la t0, pagetable_l0
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li t1, PAGE_SIZE
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mulw t1, t1, a0
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add t0, t0, t1
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la t0, pagetable_l1
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csrw sptbr, t0
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/* Page tables END */
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/* Configure mstatus */
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li s0, ((MSTATUS_VM_SV48 << MSTATUS_VM_SHIFT) | \
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li s0, ((MSTATUS_VM_SV39 << MSTATUS_VM_SHIFT) | \
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(MSTATUS_PRV_M << MSTATUS_PRV_SHIFT) | \
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(MSTATUS_PRV_S << MSTATUS_PRV1_SHIFT) | \
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(MSTATUS_PRV_U << MSTATUS_PRV2_SHIFT));
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@ -93,7 +93,6 @@ __FBSDID("$FreeBSD$");
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#endif
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struct pcpu __pcpu[MAXCPU];
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extern uint64_t pagetable_l0;
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static struct trapframe proc0_tf;
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@ -390,12 +389,6 @@ cpu_est_clockrate(int cpu_id, uint64_t *rate)
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void
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cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
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{
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uint64_t addr;
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addr = (uint64_t)&pagetable_l0;
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addr += (cpuid * PAGE_SIZE);
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pcpu->pc_sptbr = addr;
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}
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void
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@ -207,6 +207,12 @@ __FBSDID("$FreeBSD$");
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#define VM_PAGE_TO_PV_LIST_LOCK(m) \
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PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
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/* The list of all the pmaps */
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static SLIST_HEAD(, pmap_list_entry) pmap_list =
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SLIST_HEAD_INITIALIZER(pmap_list);
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static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
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struct pmap kernel_pmap_store;
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vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
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@ -304,7 +310,8 @@ pmap_l2(pmap_t pmap, vm_offset_t va)
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pd_entry_t *l1;
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l1 = pmap_l1(pmap, va);
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if (l1 == NULL)
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return (NULL);
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if ((pmap_load(l1) & PTE_VALID) == 0)
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return (NULL);
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if ((pmap_load(l1) & PTE_TYPE_M) != (PTE_TYPE_PTR << PTE_TYPE_S))
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@ -335,7 +342,7 @@ pmap_l3(pmap_t pmap, vm_offset_t va)
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return (NULL);
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if ((pmap_load(l2) & PTE_VALID) == 0)
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return (NULL);
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if (l2 == NULL || (pmap_load(l2) & PTE_TYPE_M) != (PTE_TYPE_PTR << PTE_TYPE_S))
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if ((pmap_load(l2) & PTE_TYPE_M) != (PTE_TYPE_PTR << PTE_TYPE_S))
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return (NULL);
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return (pmap_l2_to_l3(l2, va));
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@ -405,6 +412,28 @@ pmap_resident_count_dec(pmap_t pmap, int count)
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pmap->pm_stats.resident_count -= count;
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}
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static void
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pmap_distribute_l1(struct pmap *pmap, vm_pindex_t l1index,
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pt_entry_t entry)
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{
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struct pmap_list_entry *p_entry;
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struct pmap *user_pmap;
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pd_entry_t *l1;
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/* Distribute new kernel L1 entry to all the user pmaps */
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if (pmap != kernel_pmap)
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return;
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SLIST_FOREACH(p_entry, &pmap_list, pmap_link) {
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user_pmap = p_entry->pmap;
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l1 = &user_pmap->pm_l1[l1index];
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if (entry)
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pmap_load_store(l1, entry);
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else
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pmap_load_clear(l1);
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}
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}
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static pt_entry_t *
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pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
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u_int *l2_slot)
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@ -462,10 +491,9 @@ pmap_bootstrap_dmap(vm_offset_t l1pt, vm_paddr_t kernstart)
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KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
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/* superpages */
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pn = ((pa >> L1_SHIFT) & Ln_ADDR_MASK);
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pn = (pa / PAGE_SIZE);
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entry = (PTE_VALID | (PTE_TYPE_SRWX << PTE_TYPE_S));
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entry |= (pn << PTE_PPN2_S);
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entry |= (pn << PTE_PPN0_S);
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pmap_load_store(&l1[l1_slot], entry);
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}
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@ -473,6 +501,44 @@ pmap_bootstrap_dmap(vm_offset_t l1pt, vm_paddr_t kernstart)
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cpu_tlb_flushID();
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}
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static vm_offset_t
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pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
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{
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vm_offset_t l2pt, l3pt;
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pt_entry_t entry;
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pd_entry_t *l2;
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vm_paddr_t pa;
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u_int l2_slot;
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pn_t pn;
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KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
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l2 = pmap_l2(kernel_pmap, va);
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l2 = (pd_entry_t *)((uintptr_t)l2 & ~(PAGE_SIZE - 1));
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l2pt = (vm_offset_t)l2;
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l2_slot = pmap_l2_index(va);
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l3pt = l3_start;
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for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
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KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
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pa = pmap_early_vtophys(l1pt, l3pt);
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pn = (pa / PAGE_SIZE);
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entry = (PTE_VALID | (PTE_TYPE_PTR << PTE_TYPE_S));
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entry |= (pn << PTE_PPN0_S);
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pmap_load_store(&l2[l2_slot], entry);
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l3pt += PAGE_SIZE;
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}
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/* Clean the L2 page table */
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memset((void *)l3_start, 0, l3pt - l3_start);
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cpu_dcache_wb_range(l3_start, l3pt - l3_start);
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cpu_dcache_wb_range((vm_offset_t)l2, PAGE_SIZE);
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return l3pt;
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}
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/*
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* Bootstrap the system enough to run with virtual memory.
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*/
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@ -578,6 +644,10 @@ pmap_bootstrap(vm_offset_t l1pt, vm_paddr_t kernstart, vm_size_t kernlen)
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freemempos = KERNBASE + kernlen;
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freemempos = roundup2(freemempos, PAGE_SIZE);
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/* Create the l3 tables for the early devmap */
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freemempos = pmap_bootstrap_l3(l1pt,
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VM_MAX_KERNEL_ADDRESS - L2_SIZE, freemempos);
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cpu_tlb_flushID();
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#define alloc_pages(var, np) \
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@ -815,10 +885,10 @@ pmap_kextract(vm_offset_t va)
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void
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pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
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{
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pt_entry_t entry;
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pt_entry_t *l3;
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vm_offset_t va;
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panic("%s: implement me\n", __func__);
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pn_t pn;
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KASSERT((pa & L3_OFFSET) == 0,
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("pmap_kenter_device: Invalid physical address"));
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@ -831,11 +901,12 @@ pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
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while (size != 0) {
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l3 = pmap_l3(kernel_pmap, va);
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KASSERT(l3 != NULL, ("Invalid page table, va: 0x%lx", va));
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panic("%s: unimplemented", __func__);
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#if 0 /* implement me */
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pmap_load_store(l3, (pa & ~L3_OFFSET) | ATTR_DEFAULT |
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ATTR_IDX(DEVICE_MEMORY) | L3_PAGE);
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#endif
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pn = (pa / PAGE_SIZE);
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entry = (PTE_VALID | (PTE_TYPE_SRWX << PTE_TYPE_S));
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entry |= (pn << PTE_PPN0_S);
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pmap_load_store(l3, entry);
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PTE_SYNC(l3);
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va += PAGE_SIZE;
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@ -1037,6 +1108,7 @@ _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
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pd_entry_t *l1;
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l1 = pmap_l1(pmap, va);
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pmap_load_clear(l1);
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pmap_distribute_l1(pmap, pmap_l1_index(va), 0);
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PTE_SYNC(l1);
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} else {
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/* PTE page */
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@ -1105,6 +1177,7 @@ pmap_pinit0(pmap_t pmap)
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int
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pmap_pinit(pmap_t pmap)
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{
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struct pmap_list_entry *p_entry;
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vm_paddr_t l1phys;
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vm_page_t l1pt;
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@ -1123,6 +1196,16 @@ pmap_pinit(pmap_t pmap)
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bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
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/* Install kernel pagetables */
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memcpy(pmap->pm_l1, kernel_pmap->pm_l1, PAGE_SIZE);
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p_entry = malloc(sizeof(struct pmap_list_entry), M_VMPMAP, M_WAITOK);
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p_entry->pmap = pmap;
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pmap->p_entry = p_entry;
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/* Add to the list of all pmaps */
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SLIST_INSERT_HEAD(&pmap_list, p_entry, pmap_link);
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return (1);
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}
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@ -1187,6 +1270,7 @@ _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
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entry = (PTE_VALID | (PTE_TYPE_PTR << PTE_TYPE_S));
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entry |= (pn << PTE_PPN0_S);
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pmap_load_store(l1, entry);
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pmap_distribute_l1(pmap, l1index, entry);
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PTE_SYNC(l1);
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@ -1289,6 +1373,13 @@ pmap_release(pmap_t pmap)
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m->wire_count--;
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atomic_subtract_int(&vm_cnt.v_wire_count, 1);
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vm_page_free_zero(m);
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/* Remove kernel pagetables */
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bzero(pmap->pm_l1, PAGE_SIZE);
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/* Remove pmap from the all pmaps list */
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SLIST_REMOVE(&pmap_list, pmap->p_entry,
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pmap_list_entry, pmap_link);
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}
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#if 0
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||||
@ -1347,6 +1438,8 @@ pmap_growkernel(vm_offset_t addr)
|
||||
entry = (PTE_VALID | (PTE_TYPE_PTR << PTE_TYPE_S));
|
||||
entry |= (pn << PTE_PPN0_S);
|
||||
pmap_load_store(l1, entry);
|
||||
pmap_distribute_l1(kernel_pmap,
|
||||
pmap_l1_index(kernel_vm_end), entry);
|
||||
|
||||
PTE_SYNC(l1);
|
||||
continue; /* try again */
|
||||
@ -2003,6 +2096,7 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
|
||||
entry = (PTE_VALID | (PTE_TYPE_PTR << PTE_TYPE_S));
|
||||
entry |= (l2_pn << PTE_PPN0_S);
|
||||
pmap_load_store(l1, entry);
|
||||
pmap_distribute_l1(pmap, pmap_l1_index(va), entry);
|
||||
PTE_SYNC(l1);
|
||||
|
||||
l2 = pmap_l1_to_l2(l1, va);
|
||||
@ -3085,18 +3179,13 @@ pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
|
||||
void
|
||||
pmap_activate(struct thread *td)
|
||||
{
|
||||
pt_entry_t entry;
|
||||
pn_t pn;
|
||||
pmap_t pmap;
|
||||
|
||||
critical_enter();
|
||||
pmap = vmspace_pmap(td->td_proc->p_vmspace);
|
||||
td->td_pcb->pcb_l1addr = vtophys(pmap->pm_l1);
|
||||
|
||||
pn = (td->td_pcb->pcb_l1addr / PAGE_SIZE);
|
||||
entry = (PTE_VALID | (PTE_TYPE_PTR << PTE_TYPE_S));
|
||||
entry |= (pn << PTE_PPN0_S);
|
||||
pmap_load_store((uint64_t *)PCPU_GET(sptbr), entry);
|
||||
__asm __volatile("csrw sptbr, %0" :: "r"(td->td_pcb->pcb_l1addr));
|
||||
|
||||
pmap_invalidate_all(pmap);
|
||||
critical_exit();
|
||||
|
||||
@ -55,14 +55,8 @@ ENTRY(cpu_throw)
|
||||
sfence.vm
|
||||
|
||||
/* Switch to the new pmap */
|
||||
ld t1, PCB_L1ADDR(x13) /* Link to next level PN */
|
||||
srli t1, t1, PAGE_SHIFT /* PN no */
|
||||
li t2, (PTE_VALID | (PTE_TYPE_PTR << PTE_TYPE_S))
|
||||
slli t3, t1, PTE_PPN0_S /* (t1 << PTE_PPN0_S) */
|
||||
or t4, t2, t3
|
||||
/* Store single level0 PTE entry to position */
|
||||
ld t0, PC_SPTBR(gp)
|
||||
sd t4, 0(t0)
|
||||
ld t0, PCB_L1ADDR(x13)
|
||||
csrw sptbr, t0
|
||||
|
||||
/* TODO: Invalidate the TLB */
|
||||
|
||||
@ -140,14 +134,8 @@ ENTRY(cpu_switch)
|
||||
sfence.vm
|
||||
|
||||
/* Switch to the new pmap */
|
||||
ld t1, PCB_L1ADDR(x13) /* Link to next level PN */
|
||||
srli t1, t1, PAGE_SHIFT /* PN no */
|
||||
li t2, (PTE_VALID | (PTE_TYPE_PTR << PTE_TYPE_S))
|
||||
slli t3, t1, PTE_PPN0_S /* (t1 << PTE_PPN0_S) */
|
||||
or t4, t2, t3
|
||||
/* Store single level0 PTE entry to position */
|
||||
ld t0, PC_SPTBR(gp)
|
||||
sd t4, 0(t0)
|
||||
ld t0, PCB_L1ADDR(x13)
|
||||
csrw sptbr, t0
|
||||
|
||||
/* TODO: Invalidate the TLB */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user