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arm64: rockchip: clk: Set the write mask when setting the clock mux

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RockChip clocks have a write mask in the upper 16bits of the mux register
which wasn't set in the set_mux function.
Also the wrong parent was tested instead of the real current one, when
switch parent, test with the current one before.

Pointy Hat:    manu
MFC after:	1 week
This commit is contained in:
manu 2019-02-25 17:40:00 +00:00
parent d5e105e787
commit 10e5aeb6eb
1 changed files with 2 additions and 1 deletions
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3
sys/arm64/rockchip/clk/rk_clk_composite.c
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@ -128,7 +128,7 @@ rk_clk_composite_set_mux(struct clknode *clk, int index)
READ4(clk, sc->muxdiv_offset, &val);
val &= ~sc->mux_mask;
val |= index << sc->mux_shift;
WRITE4(clk, sc->muxdiv_offset, val);
WRITE4(clk, sc->muxdiv_offset, val | RK_CLK_COMPOSITE_MASK);
DEVICE_UNLOCK(clk);
return (0);
@ -222,6 +222,7 @@ rk_clk_composite_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
return (0);
}
p_idx = clknode_get_parent_idx(clk);
if (p_idx != best_parent)
clknode_set_parent_by_idx(clk, best_parent);