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Compensate for half/quarter rate differences in MAC clock speed.

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This fixes the incorrect slot (and likely ACK/RTS timeout) values
which I see when enabling half/quarter rate support on the AR9280.

The resulting math matches the expected calculated default values.
This commit is contained in:
Adrian Chadd 2012-09-13 07:17:29 +00:00
parent 8a7ba352b0
commit 1690edb32c
1 changed files with 7 additions and 0 deletions
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7
sys/dev/ath/ath_hal/ah.c
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@ -514,6 +514,13 @@ ath_hal_mac_clks(struct ath_hal *ah, u_int usecs)
clks <<= 1;
} else
clks = usecs * CLOCK_RATE[WIRELESS_MODE_11b];
/* Compensate for half/quarter rate */
if (c != AH_NULL && IEEE80211_IS_CHAN_HALF(c))
clks = clks / 2;
else if (c != AH_NULL && IEEE80211_IS_CHAN_QUARTER(c))
clks = clks / 4;
return clks;
}