Add board support for the TP-Link TL-WR1043nd v2.
This is a QCA9558 based design with on-chip 2GHz 3x3 11n wifi, AR8327N switch, 64MB RAM and 8MB flash. Of course, it runs FreeBSD.
This commit is contained in:
Adrian Chadd
parent
18a2b08e65
commit
22aeed02bf
51
sys/mips/conf/TL-WR1043NDv2
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51
sys/mips/conf/TL-WR1043NDv2
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#
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# TP-Link TL-WR1043nd v2 - based on the AP135 reference design.
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#
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# This contains a QCA9558 MIPS74k SoC with on-board 3x3 2GHz wifi,
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# 64MiB RAM and an AR8327 5-port gigabit ethernet switch.
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#
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# $FreeBSD$
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#
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# Include the default QCA955x parameters
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include "QCA955X_BASE"
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ident TL-WR1043NDv2
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# Override hints with board values
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hints "TL-WR1043NDv2.hints"
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options AR71XX_REALMEM=(64*1024*1024)
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# Options required for miiproxy and mdiobus
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options ARGE_MDIO # Export an MDIO bus separate from arge
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device miiproxy # MDIO bus <-> MII PHY rendezvous
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device etherswitch
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device arswitch
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# read MSDOS formatted disks - USB
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options MSDOSFS
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# Enable the uboot environment stuff rather then the
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# redboot stuff.
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options AR71XX_ENV_UBOOT
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# uzip - to boot natively from flash
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device geom_uncompress
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options GEOM_UNCOMPRESS
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# Used for the static uboot partition map
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device geom_map
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# yes, this board has a PCI connected atheros device
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#device ath_pci
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#options AR71XX_ATH_EEPROM
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#device firmware # Used by the above
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#options ATH_EEPROM_FIRMWARE
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# Boot off of the rootfs, as defined in the geom_map setup.
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options ROOTDEVNAME=\"ufs:map/rootfs.uncompress\"
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# Default to accept
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options IPFIREWALL_DEFAULT_TO_ACCEPT
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149
sys/mips/conf/TL-WR1043NDv2.hints
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149
sys/mips/conf/TL-WR1043NDv2.hints
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# The TP-Link 1043NDv2 is based on the AP135 with a couple of minor
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# differences - well, besides having no 11ac.
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# $FreeBSD$
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# QCA955X_ETH_CFG_RGMII_EN (1 << 0)
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hint.qca955x_gmac.0.gmac_cfg=0x1
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# mdiobus0 on arge0
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hint.argemdio.0.at="nexus0"
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hint.argemdio.0.maddr=0x19000000
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hint.argemdio.0.msize=0x1000
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hint.argemdio.0.order=0
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# mdiobus1 on arge1 - required to bring up arge1?
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hint.argemdio.1.at="nexus0"
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hint.argemdio.1.maddr=0x1a000000
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hint.argemdio.1.msize=0x1000
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hint.argemdio.1.order=0
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# AR8327 - connected via mdiobus0 on arge0
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hint.arswitch.0.at="mdio0"
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hint.arswitch.0.is_7240=0 # definitely not the internal switch!
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hint.arswitch.0.is_9340=0 # not the internal switch!
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hint.arswitch.0.numphys=5 # all ports are PHYs
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hint.arswitch.0.phy4cpu=0
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hint.arswitch.0.is_rgmii=0 # not needed
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hint.arswitch.0.is_gmii=0 # not needed
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# This is where it gets a bit odd. port 0 and port 6 are CPU ports.
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# The current code only supports one CPU port. So hm, what should
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# we do to hook PAD6 up to be RGMII but a PHY, not a MAC?
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# The other trick - how do we get arge1 (hooked up to GMAC0) to work?
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# That's currently supposed to be hooked up to CPU port 0.
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# Other AR8327 configuration parameters
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# AP136-020 parameters
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# GMAC0 AR8327 -> GMAC1 (arge1) SoC, SGMII
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# AR8327_PAD_MAC_SGMII
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hint.arswitch.0.pad.0.mode=3
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#hint.arswitch.0.pad.0.rxclk_delay_sel=0
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hint.arswitch.0.pad.0.sgmii_delay_en=1
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# GMAC6 AR8327 -> GMAC0 (arge0) SoC, RGMII
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# AR8327_PAD_MAC_RGMII
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hint.arswitch.0.pad.6.mode=6
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hint.arswitch.0.pad.6.txclk_delay_en=1
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hint.arswitch.0.pad.6.rxclk_delay_en=1
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# AR8327_CLK_DELAY_SEL1
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hint.arswitch.0.pad.6.txclk_delay_sel=1
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# AR8327_CLK_DELAY_SEL2
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hint.arswitch.0.pad.6.rxclk_delay_sel=2
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hint.arswitch.0.led.ctrl0=0xcc35cc35
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hint.arswitch.0.led.ctrl1=0xca35ca35
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hint.arswitch.0.led.ctrl2=0xc935c935
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hint.arswitch.0.led.ctrl3=0x03ffff00
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int.arswitch.0.led.open_drain=1
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# force_link=1 is required for the rest of the parameters
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# to be configured.
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hint.arswitch.0.port.0.force_link=1
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hint.arswitch.0.port.0.speed=1000
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hint.arswitch.0.port.0.duplex=1
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hint.arswitch.0.port.0.txpause=1
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hint.arswitch.0.port.0.rxpause=1
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# force_link=1 is required for the rest of the parameters
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# to be configured.
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hint.arswitch.0.port.6.force_link=1
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hint.arswitch.0.port.6.speed=1000
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hint.arswitch.0.port.6.duplex=1
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hint.arswitch.0.port.6.txpause=1
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hint.arswitch.0.port.6.rxpause=1
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# arge0 - hooked up to AR8327 GMAC6, RGMII
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# set at 1000/full to the switch.
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# so, lock both sides of this connect up to 1000/full;
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# if_arge thus wont change the PLL configuration
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# upon a link status change.
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hint.arge.0.phymask=0x0
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hint.arge.0.miimode=3 # RGMII
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hint.arge.0.media=1000
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hint.arge.0.fduplex=1
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hint.arge.0.pll_1000=0x56000000
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hint.arge.0.eeprommac=0x1f01fc00
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# arge1 - lock up to 1000/full
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hint.arge.1.phymask=0x0
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hint.arge.1.media=1000
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hint.arge.1.fduplex=1
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hint.arge.1.miimode=5 # SGMII
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hint.arge.1.pll_1000=0x03000101
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# hint.arge.1.eeprommac=0x1f01fc06
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# ath0: Where the ART is - last 64k in the flash
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hint.ath.0.eepromaddr=0x1fff0000
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hint.ath.0.eepromsize=16384
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# 128 KiB u-boot
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hint.map.0.at="flash/spi0"
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hint.map.0.start=0x00000000
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hint.map.0.end=0x00020000 # 128k u-boot
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hint.map.0.name="u-boot"
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hint.map.0.readonly=1
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# The TP-Link firmware will put the kernel first (variable size);
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# then the rootfs will be placed hopefully at a 64KiB alignment
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# by whatever calls mktplinkfw.
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hint.map.1.at="flash/spi0"
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hint.map.1.start=0x00020000
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hint.map.1.end="search:0x00020000:0x10000:.!/bin/sh"
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hint.map.1.name="kernel"
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hint.map.1.readonly=1
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hint.map.2.at="flash/spi0"
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hint.map.2.start="search:0x00020000:0x10000:.!/bin/sh"
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hint.map.2.end=0x007d0000
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hint.map.2.name="rootfs"
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hint.map.2.readonly=1
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# 64KiB cfg
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hint.map.3.at="flash/spi0"
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hint.map.3.start=0x007d0000
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hint.map.3.end=0x007e0000
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hint.map.3.name="cfg"
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hint.map.3.readonly=0
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# 64KiB mib0
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hint.map.4.at="flash/spi0"
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hint.map.4.start=0x007e0000
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hint.map.4.end=0x007f0000
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hint.map.4.name="mib0"
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hint.map.4.readonly=1
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# 64KiB ART
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hint.map.5.at="flash/spi0"
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hint.map.5.start=0x007f0000
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hint.map.5.end=0x00800000 # 64k ART
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hint.map.5.name="ART"
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hint.map.5.readonly=1
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