Retire ixgb(4)
This driver was for an early and uncommon legacy PCI 10GbE for a single ASIC, Intel 82597EX. Intel quickly shifted to the long lived ixgbe family. Submitted by: kbowling Reviewed by: brooks imp jeffrey.e.pieper@intel.com Relnotes: yes Sponsored by: Limelight Networks Differential Revision: https://reviews.freebsd.org/D15234
This commit is contained in:
Sean Bruno
parent
f2f0b02bdc
commit
2695c9c109
@ -38,6 +38,8 @@
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# xargs -n1 | sort | uniq -d;
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# xargs -n1 | sort | uniq -d;
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# done
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# done
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# 20180502: retire ixgb
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OLD_FILES+=usr/share/man/man4/ixgb.4.gz
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# 20180501: retire lmc
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# 20180501: retire lmc
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OLD_FILES+=usr/include/dev/lmc/if_lmc.h
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OLD_FILES+=usr/include/dev/lmc/if_lmc.h
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OLD_DIRS+=usr/include/dev/lmc
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OLD_DIRS+=usr/include/dev/lmc
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6
UPDATING
6
UPDATING
@ -51,6 +51,12 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 12.x IS SLOW:
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****************************** SPECIAL WARNING: ******************************
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****************************** SPECIAL WARNING: ******************************
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20180502:
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The ixgb(4) driver has been removed. This driver was for an early and
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uncommon legacy PCI 10GbE for a single ASIC, Intel 82597EX. Intel
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quickly shifted to the long lived ixgbe family. If you have device
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ixgb in your kernel config file it must be removed.
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20180501:
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20180501:
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The lmc(4) driver has been removed. This was a WAN interface
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The lmc(4) driver has been removed. This was a WAN interface
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card that was already reportedly rare in 2003, and had an ambiguous
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card that was already reportedly rare in 2003, and had an ambiguous
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@ -244,7 +244,6 @@ MAN= aac.4 \
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iwmfw.4 \
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iwmfw.4 \
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iwn.4 \
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iwn.4 \
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iwnfw.4 \
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iwnfw.4 \
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ixgb.4 \
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ixgbe.4 \
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ixgbe.4 \
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ixl.4 \
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ixl.4 \
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ixlv.4 \
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ixlv.4 \
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@ -675,7 +674,6 @@ MLINKS+=ipw.4 if_ipw.4
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MLINKS+=iwi.4 if_iwi.4
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MLINKS+=iwi.4 if_iwi.4
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MLINKS+=iwm.4 if_iwm.4
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MLINKS+=iwm.4 if_iwm.4
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MLINKS+=iwn.4 if_iwn.4
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MLINKS+=iwn.4 if_iwn.4
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MLINKS+=ixgb.4 if_ixgb.4
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MLINKS+=ixgbe.4 ix.4
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MLINKS+=ixgbe.4 ix.4
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MLINKS+=ixgbe.4 if_ix.4
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MLINKS+=ixgbe.4 if_ix.4
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MLINKS+=ixgbe.4 if_ixgbe.4
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MLINKS+=ixgbe.4 if_ixgbe.4
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@ -1,131 +0,0 @@
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.\" Copyright (c) 2001-2004, Intel Corporation
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions are met:
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.\"
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.\" 1. Redistributions of source code must retain the above copyright notice,
|
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.\" this list of conditions and the following disclaimer.
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.\"
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.\" 2. Redistributions in binary form must reproduce the above copyright
|
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.\" notice, this list of conditions and the following disclaimer in the
|
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" 3. Neither the name of the Intel Corporation nor the names of its
|
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.\" contributors may be used to endorse or promote products derived from
|
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.\" this software without specific prior written permission.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
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.\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
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.\" LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
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.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
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.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
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.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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.\" POSSIBILITY OF SUCH DAMAGE.
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.\"
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.\" * Other names and brands may be claimed as the property of others.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd April 30, 2018
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.Dt IXGB 4
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.Os
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.Sh NAME
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.Nm ixgb
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.Nd "Intel(R) PRO/10GbE Ethernet driver for the FreeBSD operating system"
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.Sh SYNOPSIS
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To compile this driver into the kernel,
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place the following line in your
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kernel configuration file:
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.Bd -ragged -offset indent
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.Cd "device ixgb"
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.Ed
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.Pp
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Alternatively, to load the driver as a
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module at boot time, place the following line in
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.Xr loader.conf 5 :
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.Bd -literal -offset indent
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if_ixgb_load="YES"
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.Ed
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.Sh DEPRECATION NOTICE
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The
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.Nm
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driver is not present in
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.Fx 12.0
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and later.
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.Sh DESCRIPTION
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The
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.Nm
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driver provides support for PCI Gigabit Ethernet adapters based on
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the Intel 82597EX Ethernet controller chips.
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The driver supports Transmit/Receive checksum offload
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and Jumbo Frames.
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.Pp
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For questions related to hardware requirements,
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refer to the documentation supplied with your Intel PRO/10GbE adapter.
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All hardware requirements listed apply to use with
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.Fx .
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.Pp
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Support for Jumbo Frames is provided via the interface MTU setting.
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Selecting an MTU larger than 1500 bytes with the
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.Xr ifconfig 8
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utility configures the adapter to receive and transmit Jumbo Frames.
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The maximum MTU size for Jumbo Frames is 16114.
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.Pp
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This driver version supports VLANs.
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For information on enabling VLANs, see
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.Xr ifconfig 8 .
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.Sh HARDWARE
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The
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.Nm
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driver supports the following cards:
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.Pp
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.Bl -bullet -compact
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.It
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Intel PRO/10GbE LR Server Adapter
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.It
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Intel PRO/10GbE SR Server Adapter
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.El
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.Sh DIAGNOSTICS
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.Bl -diag
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.It "ixgb%d: Unable to allocate bus resource: memory"
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A fatal initialization error has occurred.
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.It "ixgb%d: Unable to allocate bus resource: interrupt"
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A fatal initialization error has occurred.
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.It "ixgb%d: watchdog timeout -- resetting"
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The device has stopped responding to the network, or there is a problem with
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the network connection (cable).
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.El
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.Sh SUPPORT
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For general information and support,
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go to the Intel support website at:
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.Pa http://support.intel.com .
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.Pp
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If an issue is identified with the released source code on the supported kernel
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with a supported adapter, email the specific information related to the
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issue to
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.Aq Mt freebsd@intel.com .
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.Sh SEE ALSO
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.Xr arp 4 ,
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.Xr em 4 ,
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.Xr netintro 4 ,
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.Xr ng_ether 4 ,
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.Xr polling 4 ,
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.Xr vlan 4 ,
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.Xr ifconfig 8
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.Sh HISTORY
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The
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.Nm
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device driver first appeared in
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.Fx 4.11
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and
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.Fx 5.3 .
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.Sh AUTHORS
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The
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.Nm
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driver was written by
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.An Intel Corporation Aq Mt freebsd@intel.com .
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@ -185,7 +185,6 @@ As of this writing, the
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.Xr fwip 4 ,
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.Xr fwip 4 ,
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.Xr fxp 4 ,
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.Xr fxp 4 ,
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.Xr igb 4 ,
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.Xr igb 4 ,
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.Xr ixgb 4 ,
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.Xr nfe 4 ,
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.Xr nfe 4 ,
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.Xr nge 4 ,
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.Xr nge 4 ,
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.Xr re 4 ,
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.Xr re 4 ,
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@ -132,7 +132,6 @@ in hardware:
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.Xr cxgbe 4 ,
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.Xr cxgbe 4 ,
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.Xr em 4 ,
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.Xr em 4 ,
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.Xr igb 4 ,
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.Xr igb 4 ,
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.Xr ixgb 4 ,
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.Xr ixgbe 4 ,
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.Xr ixgbe 4 ,
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.Xr jme 4 ,
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.Xr jme 4 ,
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.Xr liquidio 4 ,
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.Xr liquidio 4 ,
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@ -2123,7 +2123,6 @@ device cxgbe # Chelsio T4-T6 1/10/25/40/100 Gigabit Ethernet
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device cxgbev # Chelsio T4-T6 Virtual Functions
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device cxgbev # Chelsio T4-T6 Virtual Functions
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device de # DEC/Intel DC21x4x (``Tulip'')
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device de # DEC/Intel DC21x4x (``Tulip'')
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device em # Intel Pro/1000 Gigabit Ethernet
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device em # Intel Pro/1000 Gigabit Ethernet
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device ixgb # Intel Pro/10Gbe PCI-X Ethernet
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device ix # Intel Pro/10Gbe PCIE Ethernet
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device ix # Intel Pro/10Gbe PCIE Ethernet
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device ixv # Intel Pro/10Gbe PCIE Ethernet VF
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device ixv # Intel Pro/10Gbe PCIE Ethernet VF
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device le # AMD Am7900 LANCE and Am79C9xx PCnet
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device le # AMD Am7900 LANCE and Am79C9xx PCnet
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@ -2264,9 +2264,6 @@ iwn6050.fw optional iwn6050fw | iwnfw \
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compile-with "${NORMAL_FW}" \
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compile-with "${NORMAL_FW}" \
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no-obj no-implicit-rule \
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no-obj no-implicit-rule \
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clean "iwn6050.fw"
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clean "iwn6050.fw"
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dev/ixgb/if_ixgb.c optional ixgb
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dev/ixgb/ixgb_ee.c optional ixgb
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dev/ixgb/ixgb_hw.c optional ixgb
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dev/ixgbe/if_ix.c optional ix inet \
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dev/ixgbe/if_ix.c optional ix inet \
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compile-with "${NORMAL_C} -I$S/dev/ixgbe -DSMP"
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compile-with "${NORMAL_C} -I$S/dev/ixgbe -DSMP"
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dev/ixgbe/if_ixv.c optional ixv inet \
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dev/ixgbe/if_ixv.c optional ixv inet \
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@ -1,33 +0,0 @@
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/*$FreeBSD$*/
|
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/*-
|
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|
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Copyright (c) 2001-2004, Intel Corporation
|
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All rights reserved.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without
|
|
||||||
modification, are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer.
|
|
||||||
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer in the
|
|
||||||
documentation and/or other materials provided with the distribution.
|
|
||||||
|
|
||||||
3. Neither the name of the Intel Corporation nor the names of its
|
|
||||||
contributors may be used to endorse or promote products derived from
|
|
||||||
this software without specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
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|
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*/
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@ -1,237 +0,0 @@
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/*$FreeBSD$*/
|
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FreeBSD Driver for Intel(R) PRO/10GbE Server Adapters
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=====================================================
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|
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March 10, 2004
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Contents
|
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========
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|
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- Overview
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- Supported Adapters
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- Building and Installation
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- Additional Configurations
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|
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|
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|
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Overview
|
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========
|
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||||||
|
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This file describes the FreeBSD* driver, version 1.0.x, for the Intel(R)
|
|
||||||
PRO/10GbE Family of Adapters. This driver has been developed for use with
|
|
||||||
FreeBSD, version 4.8 and later.
|
|
||||||
|
|
||||||
For questions related to hardware requirements, refer to the documentation
|
|
||||||
supplied with your Intel PRO/10GbE adapter. All hardware requirements listed
|
|
||||||
apply to use with FreeBSD.
|
|
||||||
|
|
||||||
|
|
||||||
|
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Supported Adapters
|
|
||||||
==================
|
|
||||||
|
|
||||||
The following Intel network adapters are compatible with the drivers in this
|
|
||||||
release:
|
|
||||||
|
|
||||||
Controller Adapter Name Physical Layer
|
|
||||||
---------- ------------ --------------
|
|
||||||
|
|
||||||
82597EX PRO/10GbE LR/SR Server Adapter 10G Base -LR and -SR
|
|
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850 and 1310 nm optical fiber
|
|
||||||
|
|
||||||
|
|
||||||
Building and Installation
|
|
||||||
=========================
|
|
||||||
|
|
||||||
NOTE: You must have kernel sources installed in order to compile the driver
|
|
||||||
module.
|
|
||||||
|
|
||||||
In the instructions below, x.x.x is the driver version as indicated in
|
|
||||||
the name of the driver tar.
|
|
||||||
|
|
||||||
|
|
||||||
1. Move the base driver tar file to the directory of your choice. For
|
|
||||||
example, use /home/username/ixgb or /usr/local/src/ixgb.
|
|
||||||
|
|
||||||
2. Untar/unzip the archive:
|
|
||||||
tar xfz ixgb-x.x.x.tar.gz
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|
||||||
|
|
||||||
3. To install man page:
|
|
||||||
cd ixgb-x.x.x
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|
||||||
gzip -c ixgb.4 > /usr/share/man/man4/ixgb.4.gz
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|
||||||
|
|
||||||
4. To load the driver onto a running system:
|
|
||||||
cd ixgb-x.x.x/src
|
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||||||
make load
|
|
||||||
|
|
||||||
5. To assign an IP address to the interface, enter the following:
|
|
||||||
ifconfig ixgb<interface_num> <IP_address>
|
|
||||||
|
|
||||||
6. Verify that the interface works. Enter the following, where <IP_address>
|
|
||||||
is the IP address for another machine on the same subnet as the interface
|
|
||||||
that is being tested:
|
|
||||||
ping <IP_address>
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|
||||||
|
|
||||||
7. If you want the driver to load automatically when the system is booted:
|
|
||||||
|
|
||||||
cd ixgb-x.x.x/src
|
|
||||||
make load
|
|
||||||
cp if_ixgb.ko /modules
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|
||||||
|
|
||||||
Edit /boot/loader.conf, and add the following line:
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|
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if_ixgb_load="YES"
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||||||
OR
|
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||||||
|
|
||||||
compile the driver into the kernel (see item 7).
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|
||||||
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|
||||||
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|
||||||
Edit /etc/rc.conf, and create the appropriate ifconfig_ixgb<interface_num>
|
|
||||||
entry:
|
|
||||||
|
|
||||||
ifconfig_ixgb<interface_num>="<ifconfig_settings>"
|
|
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|
|
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Example usage:
|
|
||||||
|
|
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ifconfig_ixgb0="inet 192.168.10.1 netmask 255.255.255.0"
|
|
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|
|
||||||
NOTE: For assistance, see the ifconfig man page.
|
|
||||||
|
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8. If you want to compile the driver into the kernel, enter:
|
|
||||||
|
|
||||||
cd ixgb-x.x.x/src
|
|
||||||
|
|
||||||
mkdir /usr/src/sys/dev/ixgb
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|
||||||
|
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||||||
cp if_ixgb* /usr/src/sys/dev/ixgb
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||||||
|
|
||||||
cp ixgb* /usr/src/sys/dev/ixgb
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|
||||||
|
|
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cp Makefile.kernel /usr/src/sys/modules/ixgb/Makefile
|
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||||||
|
|
||||||
If you have an i386 platform, you will need to edit the files.i386 file.
|
|
||||||
This is usually in /usr/src/sys/conf/; actual locations wil vary depending
|
|
||||||
on platform. Add the following lines:
|
|
||||||
|
|
||||||
dev/ixgb/ixgb_hw.c optional ixgb
|
|
||||||
dev/ixgb/ixgb_ee.c optional ixgb
|
|
||||||
dev/ixgb/if_ixgb.c optional ixgb
|
|
||||||
|
|
||||||
|
|
||||||
Remove the following lines from the files.i386 file, if they exist:
|
|
||||||
|
|
||||||
/dev/ixgb/if_ixgb_fx_hw.c optional ixgb
|
|
||||||
/dev/ixgb/if_ixgb_phy.c optional ixgb
|
|
||||||
|
|
||||||
Edit the kernel configuration file (i.e., GENERIC or MYKERNEL) in
|
|
||||||
/usr/src/sys/i386/conf, and ensure the following line is present:
|
|
||||||
|
|
||||||
device ixgb
|
|
||||||
|
|
||||||
Compile and install the kernel. The system must be reboot for the kernel
|
|
||||||
updates to take affect. For additional information on compiling the kernel,
|
|
||||||
consult the FreeBSD operating system documentation.
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Additional Configurations
|
|
||||||
=========================
|
|
||||||
|
|
||||||
The driver supports Transmit/Receive Checksum Offload and Jumbo Frames on
|
|
||||||
all PRO/10GbE adapters.
|
|
||||||
|
|
||||||
Jumbo Frames
|
|
||||||
------------
|
|
||||||
To enable Jumbo Frames, use the ifconfig utility to increase the MTU
|
|
||||||
beyond 1500 bytes.
|
|
||||||
|
|
||||||
NOTES:
|
|
||||||
- Only enable Jumbo Frames if your network infrastructure supports
|
|
||||||
them.
|
|
||||||
|
|
||||||
- The Jumbo Frames setting on the switch must be set to at least
|
|
||||||
22 bytes larger than that of the adapter.
|
|
||||||
|
|
||||||
- There are known performance issues with this driver when running
|
|
||||||
UDP traffic with Jumbo Frames.
|
|
||||||
|
|
||||||
The Jumbo Frames MTU range for Intel Adapters is 1500 to 16114. The default
|
|
||||||
MTU range is 1500. To modify the setting, enter the following:
|
|
||||||
|
|
||||||
ifconfig ixgb<interface_num> <hostname or IP address> mtu 9000
|
|
||||||
|
|
||||||
To confirm an interface's MTU value, use the ifconfig command. To confirm
|
|
||||||
the MTU used between two specific devices, use:
|
|
||||||
|
|
||||||
route get <destination_IP_address>
|
|
||||||
|
|
||||||
VLANs
|
|
||||||
-----
|
|
||||||
To create a new VLAN pseudo-interface:
|
|
||||||
|
|
||||||
ifconfig <vlan_name> create
|
|
||||||
|
|
||||||
To associate the VLAN pseudo-interface with a physical interface and
|
|
||||||
assign a VLAN ID, IP address, and netmask:
|
|
||||||
|
|
||||||
ifconfig <vlan_name> <ip_address> netmask <subnet_mask> vlan
|
|
||||||
<vlan_id> vlandev <physical_interface>
|
|
||||||
|
|
||||||
Example:
|
|
||||||
|
|
||||||
ifconfig vlan10 10.0.0.1 netmask 255.255.255.0 vlan10 vlandev ixgb0
|
|
||||||
|
|
||||||
In this example, all packets will be marked on egress with 802.1Q VLAN
|
|
||||||
tags, specifying a VLAN ID of 10.
|
|
||||||
|
|
||||||
To remove a VLAN pseudo-interface:
|
|
||||||
|
|
||||||
ifconfig <vlan_name> destroy
|
|
||||||
|
|
||||||
Polling
|
|
||||||
-------
|
|
||||||
To enable polling in the driver, add the following options to the kernel
|
|
||||||
configuration, and then recompile the kernel:
|
|
||||||
|
|
||||||
options DEVICE_POLLING
|
|
||||||
options HZ=1000
|
|
||||||
|
|
||||||
At runtime, use the following command to turn on polling mode.
|
|
||||||
|
|
||||||
ifconfig ixgb0 polling
|
|
||||||
|
|
||||||
Similarly, turn off polling mode by removing IFCAP_POLLING flag from
|
|
||||||
interface:
|
|
||||||
|
|
||||||
ifconfig ixgb0 -polling
|
|
||||||
|
|
||||||
The driver has to be built into the kernel for DEVICE POLLING to be
|
|
||||||
enabled in the driver.
|
|
||||||
|
|
||||||
Support
|
|
||||||
=======
|
|
||||||
|
|
||||||
For general information and support, go to the Intel support website at:
|
|
||||||
|
|
||||||
http://support.intel.com
|
|
||||||
|
|
||||||
If an issue is identified with the released source code on the supported
|
|
||||||
kernel with a supported adapter, email the specific information related to
|
|
||||||
the issue to freebsd@intel.com.
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
License
|
|
||||||
=======
|
|
||||||
|
|
||||||
This software program is released under the terms of a license agreement
|
|
||||||
between you ('Licensee') and Intel. Do not use or load this software or any
|
|
||||||
associated materials (collectively, the 'Software') until you have carefully
|
|
||||||
read the full terms and conditions of the LICENSE located in this software
|
|
||||||
package. By loading or using the Software, you agree to the terms of this
|
|
||||||
Agreement. If you do not agree with the terms of this Agreement, do not
|
|
||||||
install or use the Software.
|
|
||||||
|
|
||||||
* Other names and brands may be claimed as the property of others.
|
|
||||||
|
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
@ -1,384 +0,0 @@
|
|||||||
/*******************************************************************************
|
|
||||||
SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
|
|
||||||
Copyright (c) 2001-2004, Intel Corporation
|
|
||||||
All rights reserved.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without
|
|
||||||
modification, are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer.
|
|
||||||
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer in the
|
|
||||||
documentation and/or other materials provided with the distribution.
|
|
||||||
|
|
||||||
3. Neither the name of the Intel Corporation nor the names of its
|
|
||||||
contributors may be used to endorse or promote products derived from
|
|
||||||
this software without specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
|
|
||||||
***************************************************************************/
|
|
||||||
/*$FreeBSD$*/
|
|
||||||
|
|
||||||
#ifndef _IXGB_H_DEFINED_
|
|
||||||
#define _IXGB_H_DEFINED_
|
|
||||||
|
|
||||||
|
|
||||||
#include <sys/param.h>
|
|
||||||
#include <sys/systm.h>
|
|
||||||
#include <sys/mbuf.h>
|
|
||||||
#include <sys/protosw.h>
|
|
||||||
#include <sys/socket.h>
|
|
||||||
#include <sys/malloc.h>
|
|
||||||
#include <sys/module.h>
|
|
||||||
#include <sys/kernel.h>
|
|
||||||
#include <sys/sockio.h>
|
|
||||||
|
|
||||||
#include <net/if.h>
|
|
||||||
#include <net/if_var.h>
|
|
||||||
#include <net/if_arp.h>
|
|
||||||
#include <net/ethernet.h>
|
|
||||||
#include <net/if_dl.h>
|
|
||||||
#include <net/if_media.h>
|
|
||||||
#include <net/if_types.h>
|
|
||||||
|
|
||||||
#include <net/bpf.h>
|
|
||||||
#include <net/if_types.h>
|
|
||||||
#include <net/if_vlan_var.h>
|
|
||||||
|
|
||||||
#include <netinet/in_systm.h>
|
|
||||||
#include <netinet/in.h>
|
|
||||||
#include <netinet/ip.h>
|
|
||||||
#include <netinet/tcp.h>
|
|
||||||
#include <netinet/udp.h>
|
|
||||||
|
|
||||||
#include <sys/bus.h>
|
|
||||||
#include <machine/bus.h>
|
|
||||||
#include <sys/rman.h>
|
|
||||||
#include <machine/resource.h>
|
|
||||||
#if __FreeBSD_version >= 502000
|
|
||||||
#include <dev/pci/pcivar.h>
|
|
||||||
#include <dev/pci/pcireg.h>
|
|
||||||
#else
|
|
||||||
#include <pci/pcivar.h>
|
|
||||||
#include <pci/pcireg.h>
|
|
||||||
#endif
|
|
||||||
#include <sys/proc.h>
|
|
||||||
#include <sys/sysctl.h>
|
|
||||||
#include <sys/endian.h>
|
|
||||||
|
|
||||||
#include <dev/ixgb/ixgb_hw.h>
|
|
||||||
#include <dev/ixgb/ixgb_ee.h>
|
|
||||||
#include <dev/ixgb/ixgb_ids.h>
|
|
||||||
|
|
||||||
/* Tunables */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
|
|
||||||
* number of transmit descriptors allocated by the driver. Increasing this
|
|
||||||
* value allows the driver to queue more transmits. Each descriptor is 16
|
|
||||||
* bytes.
|
|
||||||
*/
|
|
||||||
#define IXGB_MAX_TXD 256
|
|
||||||
|
|
||||||
/*
|
|
||||||
* RxDescriptors Valid Range: 64-4096 Default Value: 1024 This value is the
|
|
||||||
* number of receive descriptors allocated by the driver. Increasing this
|
|
||||||
* value allows the driver to buffer more incoming packets. Each descriptor
|
|
||||||
* is 16 bytes. A receive buffer is also allocated for each descriptor. The
|
|
||||||
* maximum MTU size is 16110.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
#define IXGB_MAX_RXD 1024
|
|
||||||
|
|
||||||
/*
|
|
||||||
* TxIntDelay Valid Range: 0-65535 (0=off) Default Value: 32 This value
|
|
||||||
* delays the generation of transmit interrupts in units of 1.024
|
|
||||||
* microseconds. Transmit interrupt reduction can improve CPU efficiency if
|
|
||||||
* properly tuned for specific network traffic. If the system is reporting
|
|
||||||
* dropped transmits, this value may be set too high causing the driver to
|
|
||||||
* run out of available transmit descriptors.
|
|
||||||
*/
|
|
||||||
#define TIDV 32
|
|
||||||
|
|
||||||
/*
|
|
||||||
* RxIntDelay Valid Range: 0-65535 (0=off) Default Value: 72 This value
|
|
||||||
* delays the generation of receive interrupts in units of 1.024
|
|
||||||
* microseconds. Receive interrupt reduction can improve CPU efficiency if
|
|
||||||
* properly tuned for specific network traffic. Increasing this value adds
|
|
||||||
* extra latency to frame reception and can end up decreasing the throughput
|
|
||||||
* of TCP traffic. If the system is reporting dropped receives, this value
|
|
||||||
* may be set too high, causing the driver to run out of available receive
|
|
||||||
* descriptors.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
#define RDTR 72
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This parameter controls the maximum no of times the driver will loop in
|
|
||||||
* the isr. Minimum Value = 1
|
|
||||||
*/
|
|
||||||
#define IXGB_MAX_INTR 3
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Inform the stack about transmit checksum offload capabilities.
|
|
||||||
*/
|
|
||||||
#define IXGB_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This parameter controls the duration of transmit watchdog timer.
|
|
||||||
*/
|
|
||||||
#define IXGB_TX_TIMEOUT 5 /* set to 5 seconds */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This parameter controls when the driver calls the routine to reclaim
|
|
||||||
* transmit descriptors.
|
|
||||||
*/
|
|
||||||
#define IXGB_TX_CLEANUP_THRESHOLD IXGB_MAX_TXD / 8
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Flow Control Types.
|
|
||||||
* 1. ixgb_fc_none - Flow Control Disabled
|
|
||||||
* 2. ixgb_fc_rx_pause - Flow Control Receive Only
|
|
||||||
* 3. ixgb_fc_tx_pause - Flow Control Transmit Only
|
|
||||||
* 4. ixgb_fc_full - Flow Control Enabled
|
|
||||||
*/
|
|
||||||
#define FLOW_CONTROL_NONE ixgb_fc_none
|
|
||||||
#define FLOW_CONTROL_RX_PAUSE ixgb_fc_rx_pause
|
|
||||||
#define FLOW_CONTROL_TX_PAUSE ixgb_fc_tx_pause
|
|
||||||
#define FLOW_CONTROL_FULL ixgb_fc_full
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Set the flow control type. Assign one of the above flow control types to be enabled.
|
|
||||||
* Default Value: FLOW_CONTROL_FULL
|
|
||||||
*/
|
|
||||||
#define FLOW_CONTROL FLOW_CONTROL_FULL
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Receive Flow control low threshold (when we send a resume frame) (FCRTL)
|
|
||||||
* Valid Range: 64 - 262,136 (0x40 - 0x3FFF8, 8 byte granularity) must be
|
|
||||||
* less than high threshold by at least 8 bytes Default Value: 163,840
|
|
||||||
* (0x28000)
|
|
||||||
*/
|
|
||||||
#define FCRTL 0x28000
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Receive Flow control high threshold (when we send a pause frame) (FCRTH)
|
|
||||||
* Valid Range: 1,536 - 262,136 (0x600 - 0x3FFF8, 8 byte granularity) Default
|
|
||||||
* Value: 196,608 (0x30000)
|
|
||||||
*/
|
|
||||||
#define FCRTH 0x30000
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Flow control request timeout (how long to pause the link partner's tx)
|
|
||||||
* (PAP 15:0) Valid Range: 1 - 65535 Default Value: 256 (0x100)
|
|
||||||
*/
|
|
||||||
#define FCPAUSE 0x100
|
|
||||||
|
|
||||||
/* Tunables -- End */
|
|
||||||
|
|
||||||
|
|
||||||
#define IXGB_VENDOR_ID 0x8086
|
|
||||||
#define IXGB_MMBA 0x0010 /* Mem base address */
|
|
||||||
#define IXGB_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1))
|
|
||||||
|
|
||||||
#define IOCTL_CMD_TYPE u_long
|
|
||||||
#define MAX_NUM_MULTICAST_ADDRESSES 128
|
|
||||||
#define PCI_ANY_ID (~0U)
|
|
||||||
#define ETHER_ALIGN 2
|
|
||||||
|
|
||||||
/* Defines for printing debug information */
|
|
||||||
#define DEBUG_INIT 0
|
|
||||||
#define DEBUG_IOCTL 0
|
|
||||||
#define DEBUG_HW 0
|
|
||||||
#define _SV_ 0
|
|
||||||
|
|
||||||
#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
|
|
||||||
#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
|
|
||||||
#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
|
|
||||||
#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
|
|
||||||
#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
|
|
||||||
#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
|
|
||||||
#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
|
|
||||||
#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
|
|
||||||
#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
|
|
||||||
|
|
||||||
|
|
||||||
/* Supported RX Buffer Sizes */
|
|
||||||
#define IXGB_RXBUFFER_2048 2048
|
|
||||||
#define IXGB_RXBUFFER_4096 4096
|
|
||||||
#define IXGB_RXBUFFER_8192 8192
|
|
||||||
#define IXGB_RXBUFFER_16384 16384
|
|
||||||
|
|
||||||
#define IXGB_MAX_SCATTER 100
|
|
||||||
|
|
||||||
/*
|
|
||||||
* ******************************************************************************
|
|
||||||
* vendor_info_array
|
|
||||||
*
|
|
||||||
* This array contains the list of Subvendor/Subdevice IDs on which the driver
|
|
||||||
* should load.
|
|
||||||
*
|
|
||||||
*****************************************************************************
|
|
||||||
*/
|
|
||||||
typedef struct _ixgb_vendor_info_t {
|
|
||||||
unsigned int vendor_id;
|
|
||||||
unsigned int device_id;
|
|
||||||
unsigned int subvendor_id;
|
|
||||||
unsigned int subdevice_id;
|
|
||||||
unsigned int index;
|
|
||||||
} ixgb_vendor_info_t;
|
|
||||||
|
|
||||||
|
|
||||||
struct ixgb_buffer {
|
|
||||||
struct mbuf *m_head;
|
|
||||||
bus_dmamap_t map; /* bus_dma map for packet */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Bus dma allocation structure used by ixgb_dma_malloc and ixgb_dma_free.
|
|
||||||
*/
|
|
||||||
struct ixgb_dma_alloc {
|
|
||||||
bus_addr_t dma_paddr;
|
|
||||||
caddr_t dma_vaddr;
|
|
||||||
bus_dma_tag_t dma_tag;
|
|
||||||
bus_dmamap_t dma_map;
|
|
||||||
bus_dma_segment_t dma_seg;
|
|
||||||
bus_size_t dma_size;
|
|
||||||
int dma_nseg;
|
|
||||||
};
|
|
||||||
|
|
||||||
typedef enum _XSUM_CONTEXT_T {
|
|
||||||
OFFLOAD_NONE,
|
|
||||||
OFFLOAD_TCP_IP,
|
|
||||||
OFFLOAD_UDP_IP
|
|
||||||
} XSUM_CONTEXT_T;
|
|
||||||
|
|
||||||
/* Our adapter structure */
|
|
||||||
struct adapter {
|
|
||||||
struct ifnet *ifp;
|
|
||||||
struct adapter *next;
|
|
||||||
struct adapter *prev;
|
|
||||||
struct ixgb_hw hw;
|
|
||||||
|
|
||||||
/* FreeBSD operating-system-specific structures */
|
|
||||||
struct ixgb_osdep osdep;
|
|
||||||
device_t dev;
|
|
||||||
struct resource *res_memory;
|
|
||||||
struct resource *res_ioport;
|
|
||||||
struct resource *res_interrupt;
|
|
||||||
void *int_handler_tag;
|
|
||||||
struct ifmedia media;
|
|
||||||
struct callout timer;
|
|
||||||
int io_rid;
|
|
||||||
int tx_timer;
|
|
||||||
struct mtx mtx;
|
|
||||||
|
|
||||||
/* Info about the board itself */
|
|
||||||
u_int32_t part_num;
|
|
||||||
u_int8_t link_active;
|
|
||||||
u_int16_t link_speed;
|
|
||||||
u_int16_t link_duplex;
|
|
||||||
u_int32_t tx_int_delay;
|
|
||||||
u_int32_t tx_abs_int_delay;
|
|
||||||
u_int32_t rx_int_delay;
|
|
||||||
u_int32_t rx_abs_int_delay;
|
|
||||||
|
|
||||||
int raidc;
|
|
||||||
|
|
||||||
XSUM_CONTEXT_T active_checksum_context;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Transmit definitions
|
|
||||||
*
|
|
||||||
* We have an array of num_tx_desc descriptors (handled by the
|
|
||||||
* controller) paired with an array of tx_buffers (at
|
|
||||||
* tx_buffer_area). The index of the next available descriptor is
|
|
||||||
* next_avail_tx_desc. The number of remaining tx_desc is
|
|
||||||
* num_tx_desc_avail.
|
|
||||||
*/
|
|
||||||
struct ixgb_dma_alloc txdma; /* bus_dma glue for tx desc */
|
|
||||||
struct ixgb_tx_desc *tx_desc_base;
|
|
||||||
u_int32_t next_avail_tx_desc;
|
|
||||||
u_int32_t oldest_used_tx_desc;
|
|
||||||
volatile u_int16_t num_tx_desc_avail;
|
|
||||||
u_int16_t num_tx_desc;
|
|
||||||
u_int32_t txd_cmd;
|
|
||||||
struct ixgb_buffer *tx_buffer_area;
|
|
||||||
bus_dma_tag_t txtag; /* dma tag for tx */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Receive definitions
|
|
||||||
*
|
|
||||||
* we have an array of num_rx_desc rx_desc (handled by the controller),
|
|
||||||
* and paired with an array of rx_buffers (at rx_buffer_area). The
|
|
||||||
* next pair to check on receive is at offset next_rx_desc_to_check
|
|
||||||
*/
|
|
||||||
struct ixgb_dma_alloc rxdma; /* bus_dma glue for rx desc */
|
|
||||||
struct ixgb_rx_desc *rx_desc_base;
|
|
||||||
u_int32_t next_rx_desc_to_check;
|
|
||||||
u_int16_t num_rx_desc;
|
|
||||||
u_int32_t rx_buffer_len;
|
|
||||||
struct ixgb_buffer *rx_buffer_area;
|
|
||||||
bus_dma_tag_t rxtag; /* dma tag for Rx */
|
|
||||||
u_int32_t next_rx_desc_to_use;
|
|
||||||
|
|
||||||
|
|
||||||
/* Jumbo frame */
|
|
||||||
struct mbuf *fmp;
|
|
||||||
struct mbuf *lmp;
|
|
||||||
|
|
||||||
struct sysctl_ctx_list sysctl_ctx;
|
|
||||||
struct sysctl_oid *sysctl_tree;
|
|
||||||
|
|
||||||
/* Multicast array memory */
|
|
||||||
u_int8_t *mta;
|
|
||||||
/* Misc stats maintained by the driver */
|
|
||||||
unsigned long dropped_pkts;
|
|
||||||
unsigned long mbuf_alloc_failed;
|
|
||||||
unsigned long mbuf_cluster_failed;
|
|
||||||
unsigned long no_tx_desc_avail1;
|
|
||||||
unsigned long no_tx_desc_avail2;
|
|
||||||
unsigned long no_tx_map_avail;
|
|
||||||
unsigned long no_tx_dma_setup;
|
|
||||||
|
|
||||||
boolean_t in_detach;
|
|
||||||
|
|
||||||
/* Board specific private data */
|
|
||||||
#ifdef _SV_
|
|
||||||
struct ixgb_sv_stats {
|
|
||||||
uint64_t icr_rxdmt0;
|
|
||||||
uint64_t icr_rxo;
|
|
||||||
uint64_t icr_rxt0;
|
|
||||||
uint64_t icr_TXDW;
|
|
||||||
} sv_stats;
|
|
||||||
unsigned long no_pkts_avail;
|
|
||||||
unsigned long clean_tx_interrupts;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
struct ixgb_hw_stats stats;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define IXGB_LOCK_INIT(_sc, _name) \
|
|
||||||
mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
|
|
||||||
#define IXGB_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
|
|
||||||
#define IXGB_LOCK(_sc) mtx_lock(&(_sc)->mtx)
|
|
||||||
#define IXGB_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
|
|
||||||
#define IXGB_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
|
|
||||||
|
|
||||||
#endif /* _IXGB_H_DEFINED_ */
|
|
||||||
@ -1,121 +0,0 @@
|
|||||||
/*******************************************************************************
|
|
||||||
SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
|
|
||||||
Copyright (c) 2001-2004, Intel Corporation
|
|
||||||
All rights reserved.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without
|
|
||||||
modification, are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer.
|
|
||||||
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer in the
|
|
||||||
documentation and/or other materials provided with the distribution.
|
|
||||||
|
|
||||||
3. Neither the name of the Intel Corporation nor the names of its
|
|
||||||
contributors may be used to endorse or promote products derived from
|
|
||||||
this software without specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
|
|
||||||
***************************************************************************/
|
|
||||||
|
|
||||||
/*$FreeBSD$*/
|
|
||||||
|
|
||||||
#ifndef _FREEBSD_OS_H_
|
|
||||||
#define _FREEBSD_OS_H_
|
|
||||||
|
|
||||||
#include <sys/types.h>
|
|
||||||
#include <sys/param.h>
|
|
||||||
#include <sys/systm.h>
|
|
||||||
#include <sys/mbuf.h>
|
|
||||||
#include <sys/protosw.h>
|
|
||||||
#include <sys/socket.h>
|
|
||||||
#include <sys/malloc.h>
|
|
||||||
#include <sys/kernel.h>
|
|
||||||
#include <sys/bus.h>
|
|
||||||
#include <machine/bus.h>
|
|
||||||
#include <sys/rman.h>
|
|
||||||
#include <machine/resource.h>
|
|
||||||
#if __FreeBSD_version >= 502000
|
|
||||||
#include <dev/pci/pcivar.h>
|
|
||||||
#include <dev/pci/pcireg.h>
|
|
||||||
#else
|
|
||||||
#include <pci/pcivar.h>
|
|
||||||
#include <pci/pcireg.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define ASSERT(x) if(!(x)) panic("IXGB: x")
|
|
||||||
|
|
||||||
/* The happy-fun DELAY macro is defined in /usr/src/sys/i386/include/clock.h */
|
|
||||||
#define usec_delay(x) DELAY(x)
|
|
||||||
#define msec_delay(x) DELAY(1000*(x))
|
|
||||||
|
|
||||||
#define DBG 0
|
|
||||||
#define MSGOUT(S, A, B) printf(S "\n", A, B)
|
|
||||||
#define DEBUGFUNC(F) DEBUGOUT(F);
|
|
||||||
#if DBG
|
|
||||||
#define DEBUGOUT(S) printf(S "\n")
|
|
||||||
#define DEBUGOUT1(S,A) printf(S "\n",A)
|
|
||||||
#define DEBUGOUT2(S,A,B) printf(S "\n",A,B)
|
|
||||||
#define DEBUGOUT3(S,A,B,C) printf(S "\n",A,B,C)
|
|
||||||
#define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S "\n",A,B,C,D,E,F,G)
|
|
||||||
#else
|
|
||||||
#define DEBUGOUT(S)
|
|
||||||
#define DEBUGOUT1(S,A)
|
|
||||||
#define DEBUGOUT2(S,A,B)
|
|
||||||
#define DEBUGOUT3(S,A,B,C)
|
|
||||||
#define DEBUGOUT7(S,A,B,C,D,E,F,G)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define FALSE 0
|
|
||||||
#define TRUE 1
|
|
||||||
#define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
|
|
||||||
#define PCI_COMMAND_REGISTER PCIR_COMMAND
|
|
||||||
|
|
||||||
#define le16_to_cpu
|
|
||||||
|
|
||||||
struct ixgb_osdep
|
|
||||||
{
|
|
||||||
bus_space_tag_t mem_bus_space_tag;
|
|
||||||
bus_space_handle_t mem_bus_space_handle;
|
|
||||||
device_t dev;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define IXGB_WRITE_FLUSH(a) IXGB_READ_REG(a, STATUS)
|
|
||||||
|
|
||||||
#define IXGB_READ_REG(a, reg) (\
|
|
||||||
bus_space_read_4( ((struct ixgb_osdep *)(a)->back)->mem_bus_space_tag, \
|
|
||||||
((struct ixgb_osdep *)(a)->back)->mem_bus_space_handle, \
|
|
||||||
IXGB_##reg))
|
|
||||||
|
|
||||||
#define IXGB_WRITE_REG(a, reg, value) (\
|
|
||||||
bus_space_write_4( ((struct ixgb_osdep *)(a)->back)->mem_bus_space_tag, \
|
|
||||||
((struct ixgb_osdep *)(a)->back)->mem_bus_space_handle, \
|
|
||||||
IXGB_##reg, value))
|
|
||||||
|
|
||||||
|
|
||||||
#define IXGB_READ_REG_ARRAY(a, reg, offset) (\
|
|
||||||
bus_space_read_4( ((struct ixgb_osdep *)(a)->back)->mem_bus_space_tag, \
|
|
||||||
((struct ixgb_osdep *)(a)->back)->mem_bus_space_handle, \
|
|
||||||
(IXGB_##reg + ((offset) << 2))))
|
|
||||||
|
|
||||||
#define IXGB_WRITE_REG_ARRAY(a, reg, offset, value) (\
|
|
||||||
bus_space_write_4( ((struct ixgb_osdep *)(a)->back)->mem_bus_space_tag, \
|
|
||||||
((struct ixgb_osdep *)(a)->back)->mem_bus_space_handle, \
|
|
||||||
(IXGB_##reg + ((offset) << 2)), value))
|
|
||||||
|
|
||||||
#endif /* _FREEBSD_OS_H_ */
|
|
||||||
|
|
||||||
@ -1,782 +0,0 @@
|
|||||||
/*******************************************************************************
|
|
||||||
SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
|
|
||||||
Copyright (c) 2001-2004, Intel Corporation
|
|
||||||
All rights reserved.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without
|
|
||||||
modification, are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer.
|
|
||||||
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer in the
|
|
||||||
documentation and/or other materials provided with the distribution.
|
|
||||||
|
|
||||||
3. Neither the name of the Intel Corporation nor the names of its
|
|
||||||
contributors may be used to endorse or promote products derived from
|
|
||||||
this software without specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
|
|
||||||
*******************************************************************************/
|
|
||||||
|
|
||||||
/*$FreeBSD$*/
|
|
||||||
|
|
||||||
#include <dev/ixgb/ixgb_hw.h>
|
|
||||||
#include <dev/ixgb/ixgb_ee.h>
|
|
||||||
|
|
||||||
/* Local prototypes */
|
|
||||||
static uint16_t ixgb_shift_in_bits(struct ixgb_hw *hw);
|
|
||||||
|
|
||||||
static void ixgb_shift_out_bits(struct ixgb_hw *hw,
|
|
||||||
uint16_t data,
|
|
||||||
uint16_t count);
|
|
||||||
static void ixgb_standby_eeprom(struct ixgb_hw *hw);
|
|
||||||
|
|
||||||
static boolean_t ixgb_wait_eeprom_command(struct ixgb_hw *hw);
|
|
||||||
|
|
||||||
static void ixgb_cleanup_eeprom(struct ixgb_hw *hw);
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* Raises the EEPROM's clock input.
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
* eecd_reg - EECD's current value
|
|
||||||
*****************************************************************************/
|
|
||||||
static void
|
|
||||||
ixgb_raise_clock(struct ixgb_hw *hw,
|
|
||||||
uint32_t *eecd_reg)
|
|
||||||
{
|
|
||||||
/* Raise the clock input to the EEPROM (by setting the SK bit), and then
|
|
||||||
* wait 50 microseconds.
|
|
||||||
*/
|
|
||||||
*eecd_reg = *eecd_reg | IXGB_EECD_SK;
|
|
||||||
IXGB_WRITE_REG(hw, EECD, *eecd_reg);
|
|
||||||
usec_delay(50);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* Lowers the EEPROM's clock input.
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
* eecd_reg - EECD's current value
|
|
||||||
*****************************************************************************/
|
|
||||||
static void
|
|
||||||
ixgb_lower_clock(struct ixgb_hw *hw,
|
|
||||||
uint32_t *eecd_reg)
|
|
||||||
{
|
|
||||||
/* Lower the clock input to the EEPROM (by clearing the SK bit), and then
|
|
||||||
* wait 50 microseconds.
|
|
||||||
*/
|
|
||||||
*eecd_reg = *eecd_reg & ~IXGB_EECD_SK;
|
|
||||||
IXGB_WRITE_REG(hw, EECD, *eecd_reg);
|
|
||||||
usec_delay(50);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* Shift data bits out to the EEPROM.
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
* data - data to send to the EEPROM
|
|
||||||
* count - number of bits to shift out
|
|
||||||
*****************************************************************************/
|
|
||||||
static void
|
|
||||||
ixgb_shift_out_bits(struct ixgb_hw *hw,
|
|
||||||
uint16_t data,
|
|
||||||
uint16_t count)
|
|
||||||
{
|
|
||||||
uint32_t eecd_reg;
|
|
||||||
uint32_t mask;
|
|
||||||
|
|
||||||
/* We need to shift "count" bits out to the EEPROM. So, value in the
|
|
||||||
* "data" parameter will be shifted out to the EEPROM one bit at a time.
|
|
||||||
* In order to do this, "data" must be broken down into bits.
|
|
||||||
*/
|
|
||||||
mask = 0x01 << (count - 1);
|
|
||||||
eecd_reg = IXGB_READ_REG(hw, EECD);
|
|
||||||
eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI);
|
|
||||||
do {
|
|
||||||
/* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
|
|
||||||
* and then raising and then lowering the clock (the SK bit controls
|
|
||||||
* the clock input to the EEPROM). A "0" is shifted out to the EEPROM
|
|
||||||
* by setting "DI" to "0" and then raising and then lowering the clock.
|
|
||||||
*/
|
|
||||||
eecd_reg &= ~IXGB_EECD_DI;
|
|
||||||
|
|
||||||
if(data & mask)
|
|
||||||
eecd_reg |= IXGB_EECD_DI;
|
|
||||||
|
|
||||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
|
||||||
|
|
||||||
usec_delay(50);
|
|
||||||
|
|
||||||
ixgb_raise_clock(hw, &eecd_reg);
|
|
||||||
ixgb_lower_clock(hw, &eecd_reg);
|
|
||||||
|
|
||||||
mask = mask >> 1;
|
|
||||||
|
|
||||||
} while(mask);
|
|
||||||
|
|
||||||
/* We leave the "DI" bit set to "0" when we leave this routine. */
|
|
||||||
eecd_reg &= ~IXGB_EECD_DI;
|
|
||||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* Shift data bits in from the EEPROM
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*****************************************************************************/
|
|
||||||
static uint16_t
|
|
||||||
ixgb_shift_in_bits(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
uint32_t eecd_reg;
|
|
||||||
uint32_t i;
|
|
||||||
uint16_t data;
|
|
||||||
|
|
||||||
/* In order to read a register from the EEPROM, we need to shift 16 bits
|
|
||||||
* in from the EEPROM. Bits are "shifted in" by raising the clock input to
|
|
||||||
* the EEPROM (setting the SK bit), and then reading the value of the "DO"
|
|
||||||
* bit. During this "shifting in" process the "DI" bit should always be
|
|
||||||
* clear..
|
|
||||||
*/
|
|
||||||
|
|
||||||
eecd_reg = IXGB_READ_REG(hw, EECD);
|
|
||||||
|
|
||||||
eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI);
|
|
||||||
data = 0;
|
|
||||||
|
|
||||||
for(i = 0; i < 16; i++) {
|
|
||||||
data = data << 1;
|
|
||||||
ixgb_raise_clock(hw, &eecd_reg);
|
|
||||||
|
|
||||||
eecd_reg = IXGB_READ_REG(hw, EECD);
|
|
||||||
|
|
||||||
eecd_reg &= ~(IXGB_EECD_DI);
|
|
||||||
if(eecd_reg & IXGB_EECD_DO)
|
|
||||||
data |= 1;
|
|
||||||
|
|
||||||
ixgb_lower_clock(hw, &eecd_reg);
|
|
||||||
}
|
|
||||||
|
|
||||||
return data;
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* Prepares EEPROM for access
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*
|
|
||||||
* Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
|
|
||||||
* function should be called before issuing a command to the EEPROM.
|
|
||||||
*****************************************************************************/
|
|
||||||
static void
|
|
||||||
ixgb_setup_eeprom(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
uint32_t eecd_reg;
|
|
||||||
|
|
||||||
eecd_reg = IXGB_READ_REG(hw, EECD);
|
|
||||||
|
|
||||||
/* Clear SK and DI */
|
|
||||||
eecd_reg &= ~(IXGB_EECD_SK | IXGB_EECD_DI);
|
|
||||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
|
||||||
|
|
||||||
/* Set CS */
|
|
||||||
eecd_reg |= IXGB_EECD_CS;
|
|
||||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* Returns EEPROM to a "standby" state
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*****************************************************************************/
|
|
||||||
static void
|
|
||||||
ixgb_standby_eeprom(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
uint32_t eecd_reg;
|
|
||||||
|
|
||||||
eecd_reg = IXGB_READ_REG(hw, EECD);
|
|
||||||
|
|
||||||
/* Deselct EEPROM */
|
|
||||||
eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK);
|
|
||||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
|
||||||
usec_delay(50);
|
|
||||||
|
|
||||||
/* Clock high */
|
|
||||||
eecd_reg |= IXGB_EECD_SK;
|
|
||||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
|
||||||
usec_delay(50);
|
|
||||||
|
|
||||||
/* Select EEPROM */
|
|
||||||
eecd_reg |= IXGB_EECD_CS;
|
|
||||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
|
||||||
usec_delay(50);
|
|
||||||
|
|
||||||
/* Clock low */
|
|
||||||
eecd_reg &= ~IXGB_EECD_SK;
|
|
||||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
|
||||||
usec_delay(50);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* Raises then lowers the EEPROM's clock pin
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*****************************************************************************/
|
|
||||||
static void
|
|
||||||
ixgb_clock_eeprom(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
uint32_t eecd_reg;
|
|
||||||
|
|
||||||
eecd_reg = IXGB_READ_REG(hw, EECD);
|
|
||||||
|
|
||||||
/* Rising edge of clock */
|
|
||||||
eecd_reg |= IXGB_EECD_SK;
|
|
||||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
|
||||||
usec_delay(50);
|
|
||||||
|
|
||||||
/* Falling edge of clock */
|
|
||||||
eecd_reg &= ~IXGB_EECD_SK;
|
|
||||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
|
||||||
usec_delay(50);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* Terminates a command by lowering the EEPROM's chip select pin
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*****************************************************************************/
|
|
||||||
static void
|
|
||||||
ixgb_cleanup_eeprom(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
uint32_t eecd_reg;
|
|
||||||
|
|
||||||
eecd_reg = IXGB_READ_REG(hw, EECD);
|
|
||||||
|
|
||||||
eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_DI);
|
|
||||||
|
|
||||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
|
||||||
|
|
||||||
ixgb_clock_eeprom(hw);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* Waits for the EEPROM to finish the current command.
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*
|
|
||||||
* The command is done when the EEPROM's data out pin goes high.
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* TRUE: EEPROM data pin is high before timeout.
|
|
||||||
* FALSE: Time expired.
|
|
||||||
*****************************************************************************/
|
|
||||||
static boolean_t
|
|
||||||
ixgb_wait_eeprom_command(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
uint32_t eecd_reg;
|
|
||||||
uint32_t i;
|
|
||||||
|
|
||||||
|
|
||||||
/* Toggle the CS line. This in effect tells to EEPROM to actually execute
|
|
||||||
* the command in question.
|
|
||||||
*/
|
|
||||||
ixgb_standby_eeprom(hw);
|
|
||||||
|
|
||||||
/* Now read DO repeatedly until is high (equal to '1'). The EEEPROM will
|
|
||||||
* signal that the command has been completed by raising the DO signal.
|
|
||||||
* If DO does not go high in 10 milliseconds, then error out.
|
|
||||||
*/
|
|
||||||
for(i = 0; i < 200; i++) {
|
|
||||||
eecd_reg = IXGB_READ_REG(hw, EECD);
|
|
||||||
|
|
||||||
if(eecd_reg & IXGB_EECD_DO)
|
|
||||||
return (TRUE);
|
|
||||||
|
|
||||||
usec_delay(50);
|
|
||||||
}
|
|
||||||
ASSERT(0);
|
|
||||||
return (FALSE);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* Verifies that the EEPROM has a valid checksum
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*
|
|
||||||
* Reads the first 64 16 bit words of the EEPROM and sums the values read.
|
|
||||||
* If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
|
|
||||||
* valid.
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* TRUE: Checksum is valid
|
|
||||||
* FALSE: Checksum is not valid.
|
|
||||||
*****************************************************************************/
|
|
||||||
boolean_t
|
|
||||||
ixgb_validate_eeprom_checksum(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
uint16_t checksum = 0;
|
|
||||||
uint16_t i;
|
|
||||||
|
|
||||||
for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++)
|
|
||||||
checksum += ixgb_read_eeprom(hw, i);
|
|
||||||
|
|
||||||
if(checksum == (uint16_t) EEPROM_SUM)
|
|
||||||
return (TRUE);
|
|
||||||
else
|
|
||||||
return (FALSE);
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* Calculates the EEPROM checksum and writes it to the EEPROM
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*
|
|
||||||
* Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
|
|
||||||
* Writes the difference to word offset 63 of the EEPROM.
|
|
||||||
*****************************************************************************/
|
|
||||||
void
|
|
||||||
ixgb_update_eeprom_checksum(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
uint16_t checksum = 0;
|
|
||||||
uint16_t i;
|
|
||||||
|
|
||||||
for(i = 0; i < EEPROM_CHECKSUM_REG; i++)
|
|
||||||
checksum += ixgb_read_eeprom(hw, i);
|
|
||||||
|
|
||||||
checksum = (uint16_t) EEPROM_SUM - checksum;
|
|
||||||
|
|
||||||
ixgb_write_eeprom(hw, EEPROM_CHECKSUM_REG, checksum);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* Writes a 16 bit word to a given offset in the EEPROM.
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
* reg - offset within the EEPROM to be written to
|
|
||||||
* data - 16 bit word to be written to the EEPROM
|
|
||||||
*
|
|
||||||
* If ixgb_update_eeprom_checksum is not called after this function, the
|
|
||||||
* EEPROM will most likely contain an invalid checksum.
|
|
||||||
*
|
|
||||||
*****************************************************************************/
|
|
||||||
void
|
|
||||||
ixgb_write_eeprom(struct ixgb_hw *hw,
|
|
||||||
uint16_t offset,
|
|
||||||
uint16_t data)
|
|
||||||
{
|
|
||||||
/* Prepare the EEPROM for writing */
|
|
||||||
ixgb_setup_eeprom(hw);
|
|
||||||
|
|
||||||
/* Send the 9-bit EWEN (write enable) command to the EEPROM (5-bit opcode
|
|
||||||
* plus 4-bit dummy). This puts the EEPROM into write/erase mode.
|
|
||||||
*/
|
|
||||||
ixgb_shift_out_bits(hw, EEPROM_EWEN_OPCODE, 5);
|
|
||||||
ixgb_shift_out_bits(hw, 0, 4);
|
|
||||||
|
|
||||||
/* Prepare the EEPROM */
|
|
||||||
ixgb_standby_eeprom(hw);
|
|
||||||
|
|
||||||
/* Send the Write command (3-bit opcode + 6-bit addr) */
|
|
||||||
ixgb_shift_out_bits(hw, EEPROM_WRITE_OPCODE, 3);
|
|
||||||
ixgb_shift_out_bits(hw, offset, 6);
|
|
||||||
|
|
||||||
/* Send the data */
|
|
||||||
ixgb_shift_out_bits(hw, data, 16);
|
|
||||||
|
|
||||||
ixgb_wait_eeprom_command(hw);
|
|
||||||
|
|
||||||
/* Recover from write */
|
|
||||||
ixgb_standby_eeprom(hw);
|
|
||||||
|
|
||||||
/* Send the 9-bit EWDS (write disable) command to the EEPROM (5-bit
|
|
||||||
* opcode plus 4-bit dummy). This takes the EEPROM out of write/erase
|
|
||||||
* mode.
|
|
||||||
*/
|
|
||||||
ixgb_shift_out_bits(hw, EEPROM_EWDS_OPCODE, 5);
|
|
||||||
ixgb_shift_out_bits(hw, 0, 4);
|
|
||||||
|
|
||||||
/* Done with writing */
|
|
||||||
ixgb_cleanup_eeprom(hw);
|
|
||||||
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* Reads a 16 bit word from the EEPROM.
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
* offset - offset of 16 bit word in the EEPROM to read
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* The 16-bit value read from the eeprom
|
|
||||||
*****************************************************************************/
|
|
||||||
uint16_t
|
|
||||||
ixgb_read_eeprom(struct ixgb_hw *hw,
|
|
||||||
uint16_t offset)
|
|
||||||
{
|
|
||||||
uint16_t data;
|
|
||||||
|
|
||||||
/* Prepare the EEPROM for reading */
|
|
||||||
ixgb_setup_eeprom(hw);
|
|
||||||
|
|
||||||
/* Send the READ command (opcode + addr) */
|
|
||||||
ixgb_shift_out_bits(hw, EEPROM_READ_OPCODE, 3);
|
|
||||||
/*
|
|
||||||
* We have a 64 word EEPROM, there are 6 address bits
|
|
||||||
*/
|
|
||||||
ixgb_shift_out_bits(hw, offset, 6);
|
|
||||||
|
|
||||||
/* Read the data */
|
|
||||||
data = ixgb_shift_in_bits(hw);
|
|
||||||
|
|
||||||
/* End this read operation */
|
|
||||||
ixgb_standby_eeprom(hw);
|
|
||||||
|
|
||||||
return (data);
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* Reads eeprom and stores data in shared structure.
|
|
||||||
* Validates eeprom checksum and eeprom signature.
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* TRUE: if eeprom read is successful
|
|
||||||
* FALSE: otherwise.
|
|
||||||
*****************************************************************************/
|
|
||||||
boolean_t
|
|
||||||
ixgb_get_eeprom_data(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
uint16_t i;
|
|
||||||
uint16_t checksum = 0;
|
|
||||||
struct ixgb_ee_map_type *ee_map;
|
|
||||||
|
|
||||||
DEBUGFUNC("ixgb_get_eeprom_data");
|
|
||||||
|
|
||||||
ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
|
|
||||||
|
|
||||||
DEBUGOUT("ixgb_ee: Reading eeprom data\n");
|
|
||||||
for (i=0; i < IXGB_EEPROM_SIZE ; i++) {
|
|
||||||
uint16_t ee_data;
|
|
||||||
ee_data = ixgb_read_eeprom(hw, i);
|
|
||||||
checksum += ee_data;
|
|
||||||
hw->eeprom[i] = le16_to_cpu (ee_data);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (checksum != (uint16_t) EEPROM_SUM) {
|
|
||||||
DEBUGOUT("ixgb_ee: Checksum invalid.\n");
|
|
||||||
return (FALSE);
|
|
||||||
}
|
|
||||||
|
|
||||||
if ((ee_map->init_ctrl_reg_1 & le16_to_cpu(EEPROM_ICW1_SIGNATURE_MASK))
|
|
||||||
!= le16_to_cpu(EEPROM_ICW1_SIGNATURE_VALID)) {
|
|
||||||
DEBUGOUT("ixgb_ee: Signature invalid.\n");
|
|
||||||
return(FALSE);
|
|
||||||
}
|
|
||||||
|
|
||||||
return(TRUE);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* Local function to check if the eeprom signature is good
|
|
||||||
* If the eeprom signature is good, calls ixgb)get_eeprom_data.
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* TRUE: eeprom signature was good and the eeprom read was successful
|
|
||||||
* FALSE: otherwise.
|
|
||||||
******************************************************************************/
|
|
||||||
static boolean_t
|
|
||||||
ixgb_check_and_get_eeprom_data (struct ixgb_hw* hw)
|
|
||||||
{
|
|
||||||
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
|
|
||||||
|
|
||||||
|
|
||||||
if ((ee_map->init_ctrl_reg_1 & le16_to_cpu(EEPROM_ICW1_SIGNATURE_MASK))
|
|
||||||
== le16_to_cpu(EEPROM_ICW1_SIGNATURE_VALID)) {
|
|
||||||
return (TRUE);
|
|
||||||
} else {
|
|
||||||
return ixgb_get_eeprom_data(hw);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* return a word from the eeprom
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
* index - Offset of eeprom word
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* Word at indexed offset in eeprom, if valid, 0 otherwise.
|
|
||||||
******************************************************************************/
|
|
||||||
uint16_t
|
|
||||||
ixgb_get_eeprom_word(struct ixgb_hw *hw, uint16_t index)
|
|
||||||
{
|
|
||||||
|
|
||||||
if ((index < IXGB_EEPROM_SIZE) &&
|
|
||||||
(ixgb_check_and_get_eeprom_data (hw) == TRUE)) {
|
|
||||||
return(hw->eeprom[index]);
|
|
||||||
}
|
|
||||||
|
|
||||||
return(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* return the mac address from EEPROM
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
* mac_addr - Ethernet Address if EEPROM contents are valid, 0 otherwise
|
|
||||||
*
|
|
||||||
* Returns: None.
|
|
||||||
******************************************************************************/
|
|
||||||
void
|
|
||||||
ixgb_get_ee_mac_addr(struct ixgb_hw *hw,
|
|
||||||
uint8_t *mac_addr)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
|
|
||||||
|
|
||||||
DEBUGFUNC("ixgb_get_ee_mac_addr");
|
|
||||||
|
|
||||||
if (ixgb_check_and_get_eeprom_data (hw) == TRUE) {
|
|
||||||
for (i = 0; i < IXGB_ETH_LENGTH_OF_ADDRESS; i++) {
|
|
||||||
mac_addr[i] = ee_map->mac_addr[i];
|
|
||||||
DEBUGOUT2("mac(%d) = %.2X\n", i, mac_addr[i]);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* return the compatibility flags from EEPROM
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* compatibility flags if EEPROM contents are valid, 0 otherwise
|
|
||||||
******************************************************************************/
|
|
||||||
uint16_t
|
|
||||||
ixgb_get_ee_compatibility(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
|
|
||||||
|
|
||||||
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
|
|
||||||
return(ee_map->compatibility);
|
|
||||||
|
|
||||||
return(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* return the Printed Board Assembly number from EEPROM
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* PBA number if EEPROM contents are valid, 0 otherwise
|
|
||||||
******************************************************************************/
|
|
||||||
uint32_t
|
|
||||||
ixgb_get_ee_pba_number(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
|
|
||||||
return ( le16_to_cpu(hw->eeprom[EEPROM_PBA_1_2_REG])
|
|
||||||
| (le16_to_cpu(hw->eeprom[EEPROM_PBA_3_4_REG])<<16));
|
|
||||||
|
|
||||||
return(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* return the Initialization Control Word 1 from EEPROM
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* Initialization Control Word 1 if EEPROM contents are valid, 0 otherwise
|
|
||||||
******************************************************************************/
|
|
||||||
uint16_t
|
|
||||||
ixgb_get_ee_init_ctrl_reg_1(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
|
|
||||||
|
|
||||||
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
|
|
||||||
return(ee_map->init_ctrl_reg_1);
|
|
||||||
|
|
||||||
return(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* return the Initialization Control Word 2 from EEPROM
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* Initialization Control Word 2 if EEPROM contents are valid, 0 otherwise
|
|
||||||
******************************************************************************/
|
|
||||||
uint16_t
|
|
||||||
ixgb_get_ee_init_ctrl_reg_2(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
|
|
||||||
|
|
||||||
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
|
|
||||||
return(ee_map->init_ctrl_reg_2);
|
|
||||||
|
|
||||||
return(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* return the Subsystem Id from EEPROM
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* Subsystem Id if EEPROM contents are valid, 0 otherwise
|
|
||||||
******************************************************************************/
|
|
||||||
uint16_t
|
|
||||||
ixgb_get_ee_subsystem_id(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
|
|
||||||
|
|
||||||
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
|
|
||||||
return(ee_map->subsystem_id);
|
|
||||||
|
|
||||||
return(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* return the Sub Vendor Id from EEPROM
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* Sub Vendor Id if EEPROM contents are valid, 0 otherwise
|
|
||||||
******************************************************************************/
|
|
||||||
uint16_t
|
|
||||||
ixgb_get_ee_subvendor_id(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
|
|
||||||
|
|
||||||
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
|
|
||||||
return(ee_map->subvendor_id);
|
|
||||||
|
|
||||||
return(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* return the Device Id from EEPROM
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* Device Id if EEPROM contents are valid, 0 otherwise
|
|
||||||
******************************************************************************/
|
|
||||||
uint16_t
|
|
||||||
ixgb_get_ee_device_id(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
|
|
||||||
|
|
||||||
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
|
|
||||||
return(ee_map->device_id);
|
|
||||||
|
|
||||||
return(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* return the Vendor Id from EEPROM
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* Device Id if EEPROM contents are valid, 0 otherwise
|
|
||||||
******************************************************************************/
|
|
||||||
uint16_t
|
|
||||||
ixgb_get_ee_vendor_id(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
|
|
||||||
|
|
||||||
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
|
|
||||||
return(ee_map->vendor_id);
|
|
||||||
|
|
||||||
return(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* return the Software Defined Pins Register from EEPROM
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* SDP Register if EEPROM contents are valid, 0 otherwise
|
|
||||||
******************************************************************************/
|
|
||||||
uint16_t
|
|
||||||
ixgb_get_ee_swdpins_reg(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
|
|
||||||
|
|
||||||
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
|
|
||||||
return(ee_map->swdpins_reg);
|
|
||||||
|
|
||||||
return(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* return the D3 Power Management Bits from EEPROM
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* D3 Power Management Bits if EEPROM contents are valid, 0 otherwise
|
|
||||||
******************************************************************************/
|
|
||||||
uint8_t
|
|
||||||
ixgb_get_ee_d3_power(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
|
|
||||||
|
|
||||||
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
|
|
||||||
return(ee_map->d3_power);
|
|
||||||
|
|
||||||
return(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
* return the D0 Power Management Bits from EEPROM
|
|
||||||
*
|
|
||||||
* hw - Struct containing variables accessed by shared code
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* D0 Power Management Bits if EEPROM contents are valid, 0 otherwise
|
|
||||||
******************************************************************************/
|
|
||||||
uint8_t
|
|
||||||
ixgb_get_ee_d0_power(struct ixgb_hw *hw)
|
|
||||||
{
|
|
||||||
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *) hw->eeprom;
|
|
||||||
|
|
||||||
if (ixgb_check_and_get_eeprom_data (hw) == TRUE)
|
|
||||||
return(ee_map->d0_power);
|
|
||||||
|
|
||||||
return(0);
|
|
||||||
}
|
|
||||||
@ -1,118 +0,0 @@
|
|||||||
/*******************************************************************************
|
|
||||||
SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
|
|
||||||
Copyright (c) 2001-2004, Intel Corporation
|
|
||||||
All rights reserved.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without
|
|
||||||
modification, are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer.
|
|
||||||
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer in the
|
|
||||||
documentation and/or other materials provided with the distribution.
|
|
||||||
|
|
||||||
3. Neither the name of the Intel Corporation nor the names of its
|
|
||||||
contributors may be used to endorse or promote products derived from
|
|
||||||
this software without specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
|
|
||||||
*******************************************************************************/
|
|
||||||
|
|
||||||
/*$FreeBSD$*/
|
|
||||||
#ifndef _IXGB_EE_H_
|
|
||||||
#define _IXGB_EE_H_
|
|
||||||
|
|
||||||
|
|
||||||
#define IXGB_EEPROM_SIZE 64 /* Size in words */
|
|
||||||
|
|
||||||
#define IXGB_ETH_LENGTH_OF_ADDRESS 6
|
|
||||||
|
|
||||||
|
|
||||||
/* EEPROM Commands */
|
|
||||||
#define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */
|
|
||||||
#define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */
|
|
||||||
#define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */
|
|
||||||
#define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */
|
|
||||||
#define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */
|
|
||||||
|
|
||||||
/* EEPROM MAP (Word Offsets) */
|
|
||||||
#define EEPROM_IA_1_2_REG 0x0000
|
|
||||||
#define EEPROM_IA_3_4_REG 0x0001
|
|
||||||
#define EEPROM_IA_5_6_REG 0x0002
|
|
||||||
#define EEPROM_COMPATIBILITY_REG 0x0003
|
|
||||||
#define EEPROM_PBA_1_2_REG 0x0008
|
|
||||||
#define EEPROM_PBA_3_4_REG 0x0009
|
|
||||||
#define EEPROM_INIT_CONTROL1_REG 0x000A
|
|
||||||
#define EEPROM_SUBSYS_ID_REG 0x000B
|
|
||||||
#define EEPROM_SUBVEND_ID_REG 0x000C
|
|
||||||
#define EEPROM_DEVICE_ID_REG 0x000D
|
|
||||||
#define EEPROM_VENDOR_ID_REG 0x000E
|
|
||||||
#define EEPROM_INIT_CONTROL2_REG 0x000F
|
|
||||||
#define EEPROM_SWDPINS_REG 0x0020
|
|
||||||
#define EEPROM_CIRCUIT_CTRL_REG 0x0021
|
|
||||||
#define EEPROM_D0_D3_POWER_REG 0x0022
|
|
||||||
#define EEPROM_FLASH_VERSION 0x0032
|
|
||||||
#define EEPROM_CHECKSUM_REG 0x003F
|
|
||||||
|
|
||||||
/* Mask bits for fields in Word 0x0a of the EEPROM */
|
|
||||||
|
|
||||||
#define EEPROM_ICW1_SIGNATURE_MASK 0xC000
|
|
||||||
#define EEPROM_ICW1_SIGNATURE_VALID 0x4000
|
|
||||||
|
|
||||||
/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
|
|
||||||
#define EEPROM_SUM 0xBABA
|
|
||||||
|
|
||||||
/* EEPROM Map Sizes (Byte Counts) */
|
|
||||||
#define PBA_SIZE 4
|
|
||||||
|
|
||||||
/* EEPROM Map defines (WORD OFFSETS)*/
|
|
||||||
|
|
||||||
/* EEPROM structure */
|
|
||||||
struct ixgb_ee_map_type{
|
|
||||||
uint8_t mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS];
|
|
||||||
uint16_t compatibility;
|
|
||||||
uint16_t reserved1[4];
|
|
||||||
uint32_t pba_number;
|
|
||||||
uint16_t init_ctrl_reg_1;
|
|
||||||
uint16_t subsystem_id;
|
|
||||||
uint16_t subvendor_id;
|
|
||||||
uint16_t device_id;
|
|
||||||
uint16_t vendor_id;
|
|
||||||
uint16_t init_ctrl_reg_2;
|
|
||||||
uint16_t oem_reserved[16];
|
|
||||||
uint16_t swdpins_reg;
|
|
||||||
uint16_t circuit_ctrl_reg;
|
|
||||||
uint8_t d3_power;
|
|
||||||
uint8_t d0_power;
|
|
||||||
uint16_t reserved2[28];
|
|
||||||
uint16_t checksum;
|
|
||||||
};
|
|
||||||
|
|
||||||
/* EEPROM Functions */
|
|
||||||
uint16_t ixgb_read_eeprom(struct ixgb_hw *hw,
|
|
||||||
uint16_t reg);
|
|
||||||
|
|
||||||
boolean_t ixgb_validate_eeprom_checksum(struct ixgb_hw *hw);
|
|
||||||
|
|
||||||
void ixgb_update_eeprom_checksum(struct ixgb_hw *hw);
|
|
||||||
|
|
||||||
void ixgb_write_eeprom(struct ixgb_hw *hw,
|
|
||||||
uint16_t reg,
|
|
||||||
uint16_t data);
|
|
||||||
|
|
||||||
#endif /* IXGB_EE_H */
|
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
@ -1,858 +0,0 @@
|
|||||||
/*******************************************************************************
|
|
||||||
SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
|
|
||||||
Copyright (c) 2001-2004, Intel Corporation
|
|
||||||
All rights reserved.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without
|
|
||||||
modification, are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer.
|
|
||||||
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer in the
|
|
||||||
documentation and/or other materials provided with the distribution.
|
|
||||||
|
|
||||||
3. Neither the name of the Intel Corporation nor the names of its
|
|
||||||
contributors may be used to endorse or promote products derived from
|
|
||||||
this software without specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
|
|
||||||
*******************************************************************************/
|
|
||||||
|
|
||||||
/*$FreeBSD$*/
|
|
||||||
#ifndef _IXGB_HW_H_
|
|
||||||
#define _IXGB_HW_H_
|
|
||||||
|
|
||||||
#include <dev/ixgb/if_ixgb_osdep.h>
|
|
||||||
|
|
||||||
/* Enums */
|
|
||||||
typedef enum {
|
|
||||||
ixgb_mac_unknown = 0,
|
|
||||||
ixgb_82597,
|
|
||||||
ixgb_num_macs
|
|
||||||
} ixgb_mac_type;
|
|
||||||
|
|
||||||
/* Types of physical layer modules */
|
|
||||||
typedef enum {
|
|
||||||
ixgb_phy_type_unknown = 0,
|
|
||||||
ixgb_phy_type_g6005, /* 850nm, MM fiber, XPAK transceiver */
|
|
||||||
ixgb_phy_type_g6104, /* 1310nm, SM fiber, XPAK transceiver */
|
|
||||||
ixgb_phy_type_txn17201, /* 850nm, MM fiber, XPAK transceiver */
|
|
||||||
ixgb_phy_type_txn17401 /* 1310nm, SM fiber, XENPAK transceiver */
|
|
||||||
} ixgb_phy_type;
|
|
||||||
|
|
||||||
/* XPAK transceiver vendors, for the SR adapters */
|
|
||||||
typedef enum {
|
|
||||||
ixgb_xpak_vendor_intel,
|
|
||||||
ixgb_xpak_vendor_infineon
|
|
||||||
} ixgb_xpak_vendor;
|
|
||||||
|
|
||||||
/* Media Types */
|
|
||||||
typedef enum {
|
|
||||||
ixgb_media_type_unknown = 0,
|
|
||||||
ixgb_media_type_fiber = 1,
|
|
||||||
ixgb_num_media_types
|
|
||||||
} ixgb_media_type;
|
|
||||||
|
|
||||||
/* Flow Control Settings */
|
|
||||||
typedef enum {
|
|
||||||
ixgb_fc_none = 0,
|
|
||||||
ixgb_fc_rx_pause = 1,
|
|
||||||
ixgb_fc_tx_pause = 2,
|
|
||||||
ixgb_fc_full = 3,
|
|
||||||
ixgb_fc_default = 0xFF
|
|
||||||
} ixgb_fc_type;
|
|
||||||
|
|
||||||
/* PCI bus types */
|
|
||||||
typedef enum {
|
|
||||||
ixgb_bus_type_unknown = 0,
|
|
||||||
ixgb_bus_type_pci,
|
|
||||||
ixgb_bus_type_pcix
|
|
||||||
} ixgb_bus_type;
|
|
||||||
|
|
||||||
/* PCI bus speeds */
|
|
||||||
typedef enum {
|
|
||||||
ixgb_bus_speed_unknown = 0,
|
|
||||||
ixgb_bus_speed_33,
|
|
||||||
ixgb_bus_speed_66,
|
|
||||||
ixgb_bus_speed_100,
|
|
||||||
ixgb_bus_speed_133,
|
|
||||||
ixgb_bus_speed_reserved
|
|
||||||
} ixgb_bus_speed;
|
|
||||||
|
|
||||||
/* PCI bus widths */
|
|
||||||
typedef enum {
|
|
||||||
ixgb_bus_width_unknown = 0,
|
|
||||||
ixgb_bus_width_32,
|
|
||||||
ixgb_bus_width_64
|
|
||||||
} ixgb_bus_width;
|
|
||||||
|
|
||||||
|
|
||||||
#define IXGB_ETH_LENGTH_OF_ADDRESS 6
|
|
||||||
|
|
||||||
#define IXGB_EEPROM_SIZE 64 /* Size in words */
|
|
||||||
|
|
||||||
#define SPEED_10000 10000
|
|
||||||
#define FULL_DUPLEX 2
|
|
||||||
|
|
||||||
#define MIN_NUMBER_OF_DESCRIPTORS 8
|
|
||||||
#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 /* 13 bits in RDLEN/TDLEN, 128B aligned */
|
|
||||||
|
|
||||||
#define IXGB_DELAY_BEFORE_RESET 10 /* allow 10ms after idling rx/tx units */
|
|
||||||
#define IXGB_DELAY_AFTER_RESET 1 /* allow 1ms after the reset */
|
|
||||||
#define IXGB_DELAY_AFTER_EE_RESET 10 /* allow 10ms after the EEPROM reset */
|
|
||||||
|
|
||||||
#define IXGB_DELAY_USECS_AFTER_LINK_RESET 13 /* allow 13 microseconds after the reset */
|
|
||||||
/* NOTE: this is MICROSECONDS */
|
|
||||||
#define MAX_RESET_ITERATIONS 8 /* number of iterations to get things right */
|
|
||||||
|
|
||||||
/* General Registers */
|
|
||||||
#define IXGB_CTRL0 0x00000 /* Device Control Register 0 - RW */
|
|
||||||
#define IXGB_CTRL1 0x00008 /* Device Control Register 1 - RW */
|
|
||||||
#define IXGB_STATUS 0x00010 /* Device Status Register - RO */
|
|
||||||
#define IXGB_EECD 0x00018 /* EEPROM/Flash Control/Data Register - RW */
|
|
||||||
#define IXGB_MFS 0x00020 /* Maximum Frame Size - RW */
|
|
||||||
|
|
||||||
/* Interrupt */
|
|
||||||
#define IXGB_ICR 0x00080 /* Interrupt Cause Read - R/clr */
|
|
||||||
#define IXGB_ICS 0x00088 /* Interrupt Cause Set - RW */
|
|
||||||
#define IXGB_IMS 0x00090 /* Interrupt Mask Set/Read - RW */
|
|
||||||
#define IXGB_IMC 0x00098 /* Interrupt Mask Clear - WO */
|
|
||||||
|
|
||||||
/* Receive */
|
|
||||||
#define IXGB_RCTL 0x00100 /* RX Control - RW */
|
|
||||||
#define IXGB_FCRTL 0x00108 /* Flow Control Receive Threshold Low - RW */
|
|
||||||
#define IXGB_FCRTH 0x00110 /* Flow Control Receive Threshold High - RW */
|
|
||||||
#define IXGB_RDBAL 0x00118 /* RX Descriptor Base Low - RW */
|
|
||||||
#define IXGB_RDBAH 0x0011C /* RX Descriptor Base High - RW */
|
|
||||||
#define IXGB_RDLEN 0x00120 /* RX Descriptor Length - RW */
|
|
||||||
#define IXGB_RDH 0x00128 /* RX Descriptor Head - RW */
|
|
||||||
#define IXGB_RDT 0x00130 /* RX Descriptor Tail - RW */
|
|
||||||
#define IXGB_RDTR 0x00138 /* RX Delay Timer Ring - RW */
|
|
||||||
#define IXGB_RXDCTL 0x00140 /* Receive Descriptor Control - RW */
|
|
||||||
#define IXGB_RAIDC 0x00148 /* Receive Adaptive Interrupt Delay Control - RW */
|
|
||||||
#define IXGB_RXCSUM 0x00158 /* Receive Checksum Control - RW */
|
|
||||||
#define IXGB_RA 0x00180 /* Receive Address Array Base - RW */
|
|
||||||
#define IXGB_RAL 0x00180 /* Receive Address Low [0:15] - RW */
|
|
||||||
#define IXGB_RAH 0x00184 /* Receive Address High [0:15] - RW */
|
|
||||||
#define IXGB_MTA 0x00200 /* Multicast Table Array [0:127] - RW */
|
|
||||||
#define IXGB_VFTA 0x00400 /* VLAN Filter Table Array [0:127] - RW */
|
|
||||||
#define IXGB_REQ_RX_DESCRIPTOR_MULTIPLE 8
|
|
||||||
|
|
||||||
/* Transmit */
|
|
||||||
#define IXGB_TCTL 0x00600 /* TX Control - RW */
|
|
||||||
#define IXGB_TDBAL 0x00608 /* TX Descriptor Base Low - RW */
|
|
||||||
#define IXGB_TDBAH 0x0060C /* TX Descriptor Base High - RW */
|
|
||||||
#define IXGB_TDLEN 0x00610 /* TX Descriptor Length - RW */
|
|
||||||
#define IXGB_TDH 0x00618 /* TX Descriptor Head - RW */
|
|
||||||
#define IXGB_TDT 0x00620 /* TX Descriptor Tail - RW */
|
|
||||||
#define IXGB_TIDV 0x00628 /* TX Interrupt Delay Value - RW */
|
|
||||||
#define IXGB_TXDCTL 0x00630 /* Transmit Descriptor Control - RW */
|
|
||||||
#define IXGB_TSPMT 0x00638 /* TCP Segmentation PAD & Min Threshold - RW */
|
|
||||||
#define IXGB_PAP 0x00640 /* Pause and Pace - RW */
|
|
||||||
#define IXGB_REQ_TX_DESCRIPTOR_MULTIPLE 8
|
|
||||||
|
|
||||||
/* Physical */
|
|
||||||
#define IXGB_PCSC1 0x00700 /* PCS Control 1 - RW */
|
|
||||||
#define IXGB_PCSC2 0x00708 /* PCS Control 2 - RW */
|
|
||||||
#define IXGB_PCSS1 0x00710 /* PCS Status 1 - RO */
|
|
||||||
#define IXGB_PCSS2 0x00718 /* PCS Status 2 - RO */
|
|
||||||
#define IXGB_XPCSS 0x00720 /* 10GBASE-X PCS Status (or XGXS Lane Status) - RO */
|
|
||||||
#define IXGB_UCCR 0x00728 /* Unilink Circuit Control Register */
|
|
||||||
#define IXGB_XPCSTC 0x00730 /* 10GBASE-X PCS Test Control */
|
|
||||||
#define IXGB_MACA 0x00738 /* MDI Autoscan Command and Address - RW */
|
|
||||||
#define IXGB_APAE 0x00740 /* Autoscan PHY Address Enable - RW */
|
|
||||||
#define IXGB_ARD 0x00748 /* Autoscan Read Data - RO */
|
|
||||||
#define IXGB_AIS 0x00750 /* Autoscan Interrupt Status - RO */
|
|
||||||
#define IXGB_MSCA 0x00758 /* MDI Single Command and Address - RW */
|
|
||||||
#define IXGB_MSRWD 0x00760 /* MDI Single Read and Write Data - RW, RO */
|
|
||||||
|
|
||||||
/* Wake-up */
|
|
||||||
#define IXGB_WUFC 0x00808 /* Wake Up Filter Control - RW */
|
|
||||||
#define IXGB_WUS 0x00810 /* Wake Up Status - RO */
|
|
||||||
#define IXGB_FFLT 0x01000 /* Flexible Filter Length Table - RW */
|
|
||||||
#define IXGB_FFMT 0x01020 /* Flexible Filter Mask Table - RW */
|
|
||||||
#define IXGB_FTVT 0x01420 /* Flexible Filter Value Table - RW */
|
|
||||||
|
|
||||||
/* Statistics */
|
|
||||||
#define IXGB_TPRL 0x02000 /* Total Packets Received (Low) */
|
|
||||||
#define IXGB_TPRH 0x02004 /* Total Packets Received (High) */
|
|
||||||
#define IXGB_GPRCL 0x02008 /* Good Packets Received Count (Low) */
|
|
||||||
#define IXGB_GPRCH 0x0200C /* Good Packets Received Count (High) */
|
|
||||||
#define IXGB_BPRCL 0x02010 /* Broadcast Packets Received Count (Low) */
|
|
||||||
#define IXGB_BPRCH 0x02014 /* Broadcast Packets Received Count (High) */
|
|
||||||
#define IXGB_MPRCL 0x02018 /* Multicast Packets Received Count (Low) */
|
|
||||||
#define IXGB_MPRCH 0x0201C /* Multicast Packets Received Count (High) */
|
|
||||||
#define IXGB_UPRCL 0x02020 /* Unicast Packets Received Count (Low) */
|
|
||||||
#define IXGB_UPRCH 0x02024 /* Unicast Packets Received Count (High) */
|
|
||||||
#define IXGB_VPRCL 0x02028 /* VLAN Packets Received Count (Low) */
|
|
||||||
#define IXGB_VPRCH 0x0202C /* VLAN Packets Received Count (High) */
|
|
||||||
#define IXGB_JPRCL 0x02030 /* Jumbo Packets Received Count (Low) */
|
|
||||||
#define IXGB_JPRCH 0x02034 /* Jumbo Packets Received Count (High) */
|
|
||||||
#define IXGB_GORCL 0x02038 /* Good Octets Received Count (Low) */
|
|
||||||
#define IXGB_GORCH 0x0203C /* Good Octets Received Count (High) */
|
|
||||||
#define IXGB_TORL 0x02040 /* Total Octets Received (Low) */
|
|
||||||
#define IXGB_TORH 0x02044 /* Total Octets Received (High) */
|
|
||||||
#define IXGB_RNBC 0x02048 /* Receive No Buffers Count */
|
|
||||||
#define IXGB_RUC 0x02050 /* Receive Undersize Count */
|
|
||||||
#define IXGB_ROC 0x02058 /* Receive Oversize Count */
|
|
||||||
#define IXGB_RLEC 0x02060 /* Receive Length Error Count */
|
|
||||||
#define IXGB_CRCERRS 0x02068 /* CRC Error Count */
|
|
||||||
#define IXGB_ICBC 0x02070 /* Illegal control byte in mid-packet Count */
|
|
||||||
#define IXGB_ECBC 0x02078 /* Error Control byte in mid-packet Count */
|
|
||||||
#define IXGB_MPC 0x02080 /* Missed Packets Count */
|
|
||||||
#define IXGB_TPTL 0x02100 /* Total Packets Transmitted (Low) */
|
|
||||||
#define IXGB_TPTH 0x02104 /* Total Packets Transmitted (High) */
|
|
||||||
#define IXGB_GPTCL 0x02108 /* Good Packets Transmitted Count (Low) */
|
|
||||||
#define IXGB_GPTCH 0x0210C /* Good Packets Transmitted Count (High) */
|
|
||||||
#define IXGB_BPTCL 0x02110 /* Broadcast Packets Transmitted Count (Low) */
|
|
||||||
#define IXGB_BPTCH 0x02114 /* Broadcast Packets Transmitted Count (High) */
|
|
||||||
#define IXGB_MPTCL 0x02118 /* Multicast Packets Transmitted Count (Low) */
|
|
||||||
#define IXGB_MPTCH 0x0211C /* Multicast Packets Transmitted Count (High) */
|
|
||||||
#define IXGB_UPTCL 0x02120 /* Unicast Packets Transmitted Count (Low) */
|
|
||||||
#define IXGB_UPTCH 0x02124 /* Unicast Packets Transmitted Count (High) */
|
|
||||||
#define IXGB_VPTCL 0x02128 /* VLAN Packets Transmitted Count (Low) */
|
|
||||||
#define IXGB_VPTCH 0x0212C /* VLAN Packets Transmitted Count (High) */
|
|
||||||
#define IXGB_JPTCL 0x02130 /* Jumbo Packets Transmitted Count (Low) */
|
|
||||||
#define IXGB_JPTCH 0x02134 /* Jumbo Packets Transmitted Count (High) */
|
|
||||||
#define IXGB_GOTCL 0x02138 /* Good Octets Transmitted Count (Low) */
|
|
||||||
#define IXGB_GOTCH 0x0213C /* Good Octets Transmitted Count (High) */
|
|
||||||
#define IXGB_TOTL 0x02140 /* Total Octets Transmitted Count (Low) */
|
|
||||||
#define IXGB_TOTH 0x02144 /* Total Octets Transmitted Count (High) */
|
|
||||||
#define IXGB_DC 0x02148 /* Defer Count */
|
|
||||||
#define IXGB_PLT64C 0x02150 /* Packet Transmitted was less than 64 bytes Count */
|
|
||||||
#define IXGB_TSCTC 0x02170 /* TCP Segmentation Context Transmitted Count */
|
|
||||||
#define IXGB_TSCTFC 0x02178 /* TCP Segmentation Context Tx Fail Count */
|
|
||||||
#define IXGB_IBIC 0x02180 /* Illegal byte during Idle stream count */
|
|
||||||
#define IXGB_RFC 0x02188 /* Remote Fault Count */
|
|
||||||
#define IXGB_LFC 0x02190 /* Local Fault Count */
|
|
||||||
#define IXGB_PFRC 0x02198 /* Pause Frame Receive Count */
|
|
||||||
#define IXGB_PFTC 0x021A0 /* Pause Frame Transmit Count */
|
|
||||||
#define IXGB_MCFRC 0x021A8 /* MAC Control Frames (non-Pause) Received Count */
|
|
||||||
#define IXGB_MCFTC 0x021B0 /* MAC Control Frames (non-Pause) Transmitted Count */
|
|
||||||
#define IXGB_XONRXC 0x021B8 /* XON Received Count */
|
|
||||||
#define IXGB_XONTXC 0x021C0 /* XON Transmitted Count */
|
|
||||||
#define IXGB_XOFFRXC 0x021C8 /* XOFF Received Count */
|
|
||||||
#define IXGB_XOFFTXC 0x021D0 /* XOFF Transmitted Count */
|
|
||||||
#define IXGB_RJC 0x021D8 /* Receive Jabber Count */
|
|
||||||
|
|
||||||
|
|
||||||
/* CTRL0 Bit Masks */
|
|
||||||
#define IXGB_CTRL0_LRST 0x00000008
|
|
||||||
#define IXGB_CTRL0_JFE 0x00000010
|
|
||||||
#define IXGB_CTRL0_XLE 0x00000020
|
|
||||||
#define IXGB_CTRL0_MDCS 0x00000040
|
|
||||||
#define IXGB_CTRL0_CMDC 0x00000080
|
|
||||||
#define IXGB_CTRL0_SDP0 0x00040000
|
|
||||||
#define IXGB_CTRL0_SDP1 0x00080000
|
|
||||||
#define IXGB_CTRL0_SDP2 0x00100000
|
|
||||||
#define IXGB_CTRL0_SDP3 0x00200000
|
|
||||||
#define IXGB_CTRL0_SDP0_DIR 0x00400000
|
|
||||||
#define IXGB_CTRL0_SDP1_DIR 0x00800000
|
|
||||||
#define IXGB_CTRL0_SDP2_DIR 0x01000000
|
|
||||||
#define IXGB_CTRL0_SDP3_DIR 0x02000000
|
|
||||||
#define IXGB_CTRL0_RST 0x04000000
|
|
||||||
#define IXGB_CTRL0_RPE 0x08000000
|
|
||||||
#define IXGB_CTRL0_TPE 0x10000000
|
|
||||||
#define IXGB_CTRL0_VME 0x40000000
|
|
||||||
|
|
||||||
/* CTRL1 Bit Masks */
|
|
||||||
#define IXGB_CTRL1_GPI0_EN 0x00000001
|
|
||||||
#define IXGB_CTRL1_GPI1_EN 0x00000002
|
|
||||||
#define IXGB_CTRL1_GPI2_EN 0x00000004
|
|
||||||
#define IXGB_CTRL1_GPI3_EN 0x00000008
|
|
||||||
#define IXGB_CTRL1_SDP4 0x00000010
|
|
||||||
#define IXGB_CTRL1_SDP5 0x00000020
|
|
||||||
#define IXGB_CTRL1_SDP6 0x00000040
|
|
||||||
#define IXGB_CTRL1_SDP7 0x00000080
|
|
||||||
#define IXGB_CTRL1_SDP4_DIR 0x00000100
|
|
||||||
#define IXGB_CTRL1_SDP5_DIR 0x00000200
|
|
||||||
#define IXGB_CTRL1_SDP6_DIR 0x00000400
|
|
||||||
#define IXGB_CTRL1_SDP7_DIR 0x00000800
|
|
||||||
#define IXGB_CTRL1_EE_RST 0x00002000
|
|
||||||
#define IXGB_CTRL1_RO_DIS 0x00020000
|
|
||||||
#define IXGB_CTRL1_PCIXHM_MASK 0x00C00000
|
|
||||||
#define IXGB_CTRL1_PCIXHM_1_2 0x00000000
|
|
||||||
#define IXGB_CTRL1_PCIXHM_5_8 0x00400000
|
|
||||||
#define IXGB_CTRL1_PCIXHM_3_4 0x00800000
|
|
||||||
#define IXGB_CTRL1_PCIXHM_7_8 0x00C00000
|
|
||||||
|
|
||||||
/* STATUS Bit Masks */
|
|
||||||
#define IXGB_STATUS_LU 0x00000002
|
|
||||||
#define IXGB_STATUS_AIP 0x00000004
|
|
||||||
#define IXGB_STATUS_TXOFF 0x00000010
|
|
||||||
#define IXGB_STATUS_XAUIME 0x00000020
|
|
||||||
#define IXGB_STATUS_RES 0x00000040
|
|
||||||
#define IXGB_STATUS_RIS 0x00000080
|
|
||||||
#define IXGB_STATUS_RIE 0x00000100
|
|
||||||
#define IXGB_STATUS_RLF 0x00000200
|
|
||||||
#define IXGB_STATUS_RRF 0x00000400
|
|
||||||
#define IXGB_STATUS_PCI_SPD 0x00000800
|
|
||||||
#define IXGB_STATUS_BUS64 0x00001000
|
|
||||||
#define IXGB_STATUS_PCIX_MODE 0x00002000
|
|
||||||
#define IXGB_STATUS_PCIX_SPD_MASK 0x0000C000
|
|
||||||
#define IXGB_STATUS_PCIX_SPD_66 0x00000000
|
|
||||||
#define IXGB_STATUS_PCIX_SPD_100 0x00004000
|
|
||||||
#define IXGB_STATUS_PCIX_SPD_133 0x00008000
|
|
||||||
#define IXGB_STATUS_REV_ID_MASK 0x000F0000
|
|
||||||
#define IXGB_STATUS_REV_ID_SHIFT 16
|
|
||||||
|
|
||||||
/* EECD Bit Masks */
|
|
||||||
#define IXGB_EECD_SK 0x00000001
|
|
||||||
#define IXGB_EECD_CS 0x00000002
|
|
||||||
#define IXGB_EECD_DI 0x00000004
|
|
||||||
#define IXGB_EECD_DO 0x00000008
|
|
||||||
#define IXGB_EECD_FWE_MASK 0x00000030
|
|
||||||
#define IXGB_EECD_FWE_DIS 0x00000010
|
|
||||||
#define IXGB_EECD_FWE_EN 0x00000020
|
|
||||||
|
|
||||||
/* MFS */
|
|
||||||
#define IXGB_MFS_SHIFT 16
|
|
||||||
|
|
||||||
/* Interrupt Register Bit Masks (used for ICR, ICS, IMS, and IMC) */
|
|
||||||
#define IXGB_INT_TXDW 0x00000001
|
|
||||||
#define IXGB_INT_TXQE 0x00000002
|
|
||||||
#define IXGB_INT_LSC 0x00000004
|
|
||||||
#define IXGB_INT_RXSEQ 0x00000008
|
|
||||||
#define IXGB_INT_RXDMT0 0x00000010
|
|
||||||
#define IXGB_INT_RXO 0x00000040
|
|
||||||
#define IXGB_INT_RXT0 0x00000080
|
|
||||||
#define IXGB_INT_AUTOSCAN 0x00000200
|
|
||||||
#define IXGB_INT_GPI0 0x00000800
|
|
||||||
#define IXGB_INT_GPI1 0x00001000
|
|
||||||
#define IXGB_INT_GPI2 0x00002000
|
|
||||||
#define IXGB_INT_GPI3 0x00004000
|
|
||||||
|
|
||||||
/* RCTL Bit Masks */
|
|
||||||
#define IXGB_RCTL_RXEN 0x00000002
|
|
||||||
#define IXGB_RCTL_SBP 0x00000004
|
|
||||||
#define IXGB_RCTL_UPE 0x00000008
|
|
||||||
#define IXGB_RCTL_MPE 0x00000010
|
|
||||||
#define IXGB_RCTL_RDMTS_MASK 0x00000300
|
|
||||||
#define IXGB_RCTL_RDMTS_1_2 0x00000000
|
|
||||||
#define IXGB_RCTL_RDMTS_1_4 0x00000100
|
|
||||||
#define IXGB_RCTL_RDMTS_1_8 0x00000200
|
|
||||||
#define IXGB_RCTL_MO_MASK 0x00003000
|
|
||||||
#define IXGB_RCTL_MO_47_36 0x00000000
|
|
||||||
#define IXGB_RCTL_MO_46_35 0x00001000
|
|
||||||
#define IXGB_RCTL_MO_45_34 0x00002000
|
|
||||||
#define IXGB_RCTL_MO_43_32 0x00003000
|
|
||||||
#define IXGB_RCTL_MO_SHIFT 12
|
|
||||||
#define IXGB_RCTL_BAM 0x00008000
|
|
||||||
#define IXGB_RCTL_BSIZE_MASK 0x00030000
|
|
||||||
#define IXGB_RCTL_BSIZE_2048 0x00000000
|
|
||||||
#define IXGB_RCTL_BSIZE_4096 0x00010000
|
|
||||||
#define IXGB_RCTL_BSIZE_8192 0x00020000
|
|
||||||
#define IXGB_RCTL_BSIZE_16384 0x00030000
|
|
||||||
#define IXGB_RCTL_VFE 0x00040000
|
|
||||||
#define IXGB_RCTL_CFIEN 0x00080000
|
|
||||||
#define IXGB_RCTL_CFI 0x00100000
|
|
||||||
#define IXGB_RCTL_RPDA_MASK 0x00600000
|
|
||||||
#define IXGB_RCTL_RPDA_MC_MAC 0x00000000
|
|
||||||
#define IXGB_RCTL_MC_ONLY 0x00400000
|
|
||||||
#define IXGB_RCTL_CFF 0x00800000
|
|
||||||
#define IXGB_RCTL_SECRC 0x04000000
|
|
||||||
#define IXGB_RDT_FPDB 0x80000000
|
|
||||||
|
|
||||||
#define IXGB_RCTL_IDLE_RX_UNIT 0
|
|
||||||
|
|
||||||
/* FCRTL Bit Masks */
|
|
||||||
#define IXGB_FCRTL_XONE 0x80000000
|
|
||||||
|
|
||||||
/* RXDCTL Bit Masks */
|
|
||||||
#define IXGB_RXDCTL_PTHRESH_MASK 0x000001FF
|
|
||||||
#define IXGB_RXDCTL_PTHRESH_SHIFT 0
|
|
||||||
#define IXGB_RXDCTL_HTHRESH_MASK 0x0003FE00
|
|
||||||
#define IXGB_RXDCTL_HTHRESH_SHIFT 9
|
|
||||||
#define IXGB_RXDCTL_WTHRESH_MASK 0x07FC0000
|
|
||||||
#define IXGB_RXDCTL_WTHRESH_SHIFT 18
|
|
||||||
|
|
||||||
/* RAIDC Bit Masks */
|
|
||||||
#define IXGB_RAIDC_HIGHTHRS_MASK 0x0000003F
|
|
||||||
#define IXGB_RAIDC_DELAY_MASK 0x000FF800
|
|
||||||
#define IXGB_RAIDC_DELAY_SHIFT 11
|
|
||||||
#define IXGB_RAIDC_POLL_MASK 0x1FF00000
|
|
||||||
#define IXGB_RAIDC_POLL_SHIFT 20
|
|
||||||
#define IXGB_RAIDC_RXT_GATE 0x40000000
|
|
||||||
#define IXGB_RAIDC_EN 0x80000000
|
|
||||||
|
|
||||||
#define IXGB_RAIDC_POLL_1000_INTERRUPTS_PER_SECOND 1220
|
|
||||||
#define IXGB_RAIDC_POLL_5000_INTERRUPTS_PER_SECOND 244
|
|
||||||
#define IXGB_RAIDC_POLL_10000_INTERRUPTS_PER_SECOND 122
|
|
||||||
#define IXGB_RAIDC_POLL_20000_INTERRUPTS_PER_SECOND 61
|
|
||||||
|
|
||||||
/* RXCSUM Bit Masks */
|
|
||||||
#define IXGB_RXCSUM_IPOFL 0x00000100
|
|
||||||
#define IXGB_RXCSUM_TUOFL 0x00000200
|
|
||||||
|
|
||||||
/* RAH Bit Masks */
|
|
||||||
#define IXGB_RAH_ASEL_MASK 0x00030000
|
|
||||||
#define IXGB_RAH_ASEL_DEST 0x00000000
|
|
||||||
#define IXGB_RAH_ASEL_SRC 0x00010000
|
|
||||||
#define IXGB_RAH_AV 0x80000000
|
|
||||||
|
|
||||||
/* TCTL Bit Masks */
|
|
||||||
#define IXGB_TCTL_TCE 0x00000001
|
|
||||||
#define IXGB_TCTL_TXEN 0x00000002
|
|
||||||
#define IXGB_TCTL_TPDE 0x00000004
|
|
||||||
|
|
||||||
#define IXGB_TCTL_IDLE_TX_UNIT 0
|
|
||||||
|
|
||||||
/* TXDCTL Bit Masks */
|
|
||||||
#define IXGB_TXDCTL_PTHRESH_MASK 0x0000007F
|
|
||||||
#define IXGB_TXDCTL_HTHRESH_MASK 0x00007F00
|
|
||||||
#define IXGB_TXDCTL_HTHRESH_SHIFT 8
|
|
||||||
#define IXGB_TXDCTL_WTHRESH_MASK 0x007F0000
|
|
||||||
#define IXGB_TXDCTL_WTHRESH_SHIFT 16
|
|
||||||
|
|
||||||
/* TSPMT Bit Masks */
|
|
||||||
#define IXGB_TSPMT_TSMT_MASK 0x0000FFFF
|
|
||||||
#define IXGB_TSPMT_TSPBP_MASK 0xFFFF0000
|
|
||||||
#define IXGB_TSPMT_TSPBP_SHIFT 16
|
|
||||||
|
|
||||||
/* PAP Bit Masks */
|
|
||||||
#define IXGB_PAP_TXPC_MASK 0x0000FFFF
|
|
||||||
#define IXGB_PAP_TXPV_MASK 0x000F0000
|
|
||||||
#define IXGB_PAP_TXPV_10G 0x00000000
|
|
||||||
#define IXGB_PAP_TXPV_1G 0x00010000
|
|
||||||
#define IXGB_PAP_TXPV_2G 0x00020000
|
|
||||||
#define IXGB_PAP_TXPV_3G 0x00030000
|
|
||||||
#define IXGB_PAP_TXPV_4G 0x00040000
|
|
||||||
#define IXGB_PAP_TXPV_5G 0x00050000
|
|
||||||
#define IXGB_PAP_TXPV_6G 0x00060000
|
|
||||||
#define IXGB_PAP_TXPV_7G 0x00070000
|
|
||||||
#define IXGB_PAP_TXPV_8G 0x00080000
|
|
||||||
#define IXGB_PAP_TXPV_9G 0x00090000
|
|
||||||
#define IXGB_PAP_TXPV_WAN 0x000F0000
|
|
||||||
|
|
||||||
/* PCSC1 Bit Masks */
|
|
||||||
#define IXGB_PCSC1_LOOPBACK 0x00004000
|
|
||||||
|
|
||||||
/* PCSC2 Bit Masks */
|
|
||||||
#define IXGB_PCSC2_PCS_TYPE_MASK 0x00000003
|
|
||||||
#define IXGB_PCSC2_PCS_TYPE_10GBX 0x00000001
|
|
||||||
|
|
||||||
/* PCSS1 Bit Masks */
|
|
||||||
#define IXGB_PCSS1_LOCAL_FAULT 0x00000080
|
|
||||||
#define IXGB_PCSS1_RX_LINK_STATUS 0x00000004
|
|
||||||
|
|
||||||
/* PCSS2 Bit Masks */
|
|
||||||
#define IXGB_PCSS2_DEV_PRES_MASK 0x0000C000
|
|
||||||
#define IXGB_PCSS2_DEV_PRES 0x00004000
|
|
||||||
#define IXGB_PCSS2_TX_LF 0x00000800
|
|
||||||
#define IXGB_PCSS2_RX_LF 0x00000400
|
|
||||||
#define IXGB_PCSS2_10GBW 0x00000004
|
|
||||||
#define IXGB_PCSS2_10GBX 0x00000002
|
|
||||||
#define IXGB_PCSS2_10GBR 0x00000001
|
|
||||||
|
|
||||||
/* XPCSS Bit Masks */
|
|
||||||
#define IXGB_XPCSS_ALIGN_STATUS 0x00001000
|
|
||||||
#define IXGB_XPCSS_PATTERN_TEST 0x00000800
|
|
||||||
#define IXGB_XPCSS_LANE_3_SYNC 0x00000008
|
|
||||||
#define IXGB_XPCSS_LANE_2_SYNC 0x00000004
|
|
||||||
#define IXGB_XPCSS_LANE_1_SYNC 0x00000002
|
|
||||||
#define IXGB_XPCSS_LANE_0_SYNC 0x00000001
|
|
||||||
|
|
||||||
/* XPCSTC Bit Masks */
|
|
||||||
#define IXGB_XPCSTC_BERT_TRIG 0x00200000
|
|
||||||
#define IXGB_XPCSTC_BERT_SST 0x00100000
|
|
||||||
#define IXGB_XPCSTC_BERT_PSZ_MASK 0x000C0000
|
|
||||||
#define IXGB_XPCSTC_BERT_PSZ_SHIFT 17
|
|
||||||
#define IXGB_XPCSTC_BERT_PSZ_INF 0x00000003
|
|
||||||
#define IXGB_XPCSTC_BERT_PSZ_68 0x00000001
|
|
||||||
#define IXGB_XPCSTC_BERT_PSZ_1028 0x00000000
|
|
||||||
|
|
||||||
/* MSCA bit Masks */
|
|
||||||
/* New Protocol Address */
|
|
||||||
#define IXGB_MSCA_NP_ADDR_MASK 0x0000FFFF
|
|
||||||
#define IXGB_MSCA_NP_ADDR_SHIFT 0
|
|
||||||
/* Either Device Type or Register Address,depending on ST_CODE */
|
|
||||||
#define IXGB_MSCA_DEV_TYPE_MASK 0x001F0000
|
|
||||||
#define IXGB_MSCA_DEV_TYPE_SHIFT 16
|
|
||||||
#define IXGB_MSCA_PHY_ADDR_MASK 0x03E00000
|
|
||||||
#define IXGB_MSCA_PHY_ADDR_SHIFT 21
|
|
||||||
#define IXGB_MSCA_OP_CODE_MASK 0x0C000000
|
|
||||||
/* OP_CODE == 00, Address cycle, New Protocol */
|
|
||||||
/* OP_CODE == 01, Write operation */
|
|
||||||
/* OP_CODE == 10, Read operation */
|
|
||||||
/* OP_CODE == 11, Read, auto increment, New Protocol */
|
|
||||||
#define IXGB_MSCA_ADDR_CYCLE 0x00000000
|
|
||||||
#define IXGB_MSCA_WRITE 0x04000000
|
|
||||||
#define IXGB_MSCA_READ 0x08000000
|
|
||||||
#define IXGB_MSCA_READ_AUTOINC 0x0C000000
|
|
||||||
#define IXGB_MSCA_OP_CODE_SHIFT 26
|
|
||||||
#define IXGB_MSCA_ST_CODE_MASK 0x30000000
|
|
||||||
/* ST_CODE == 00, New Protocol */
|
|
||||||
/* ST_CODE == 01, Old Protocol */
|
|
||||||
#define IXGB_MSCA_NEW_PROTOCOL 0x00000000
|
|
||||||
#define IXGB_MSCA_OLD_PROTOCOL 0x10000000
|
|
||||||
#define IXGB_MSCA_ST_CODE_SHIFT 28
|
|
||||||
/* Initiate command, self-clearing when command completes */
|
|
||||||
#define IXGB_MSCA_MDI_COMMAND 0x40000000
|
|
||||||
/*MDI In Progress Enable. */
|
|
||||||
#define IXGB_MSCA_MDI_IN_PROG_EN 0x80000000
|
|
||||||
|
|
||||||
/* MSRWD bit masks */
|
|
||||||
#define IXGB_MSRWD_WRITE_DATA_MASK 0x0000FFFF
|
|
||||||
#define IXGB_MSRWD_WRITE_DATA_SHIFT 0
|
|
||||||
#define IXGB_MSRWD_READ_DATA_MASK 0xFFFF0000
|
|
||||||
#define IXGB_MSRWD_READ_DATA_SHIFT 16
|
|
||||||
|
|
||||||
/* Definitions for the optics devices on the MDIO bus. */
|
|
||||||
#define IXGB_PHY_ADDRESS 0x0 /* Single PHY, multiple "Devices" */
|
|
||||||
|
|
||||||
/* Standard five-bit Device IDs. See IEEE 802.3ae, clause 45 */
|
|
||||||
#define MDIO_PMA_PMD_DID 0x01
|
|
||||||
#define MDIO_WIS_DID 0x02
|
|
||||||
#define MDIO_PCS_DID 0x03
|
|
||||||
#define MDIO_XGXS_DID 0x04
|
|
||||||
|
|
||||||
/* Standard PMA/PMD registers and bit definitions. */
|
|
||||||
/* Note: This is a very limited set of definitions, */
|
|
||||||
/* only implemented features are defined. */
|
|
||||||
#define MDIO_PMA_PMD_CR1 0x0000
|
|
||||||
#define MDIO_PMA_PMD_CR1_RESET 0x8000
|
|
||||||
|
|
||||||
#define MDIO_PMA_PMD_XPAK_VENDOR_NAME 0x803A /* XPAK/XENPAK devices only */
|
|
||||||
|
|
||||||
/* Vendor-specific MDIO registers */
|
|
||||||
#define G6XXX_PMA_PMD_VS1 0xC001 /* Vendor-specific register */
|
|
||||||
#define G6XXX_XGXS_XAUI_VS2 0x18 /* Vendor-specific register */
|
|
||||||
|
|
||||||
#define G6XXX_PMA_PMD_VS1_PLL_RESET 0x80
|
|
||||||
#define G6XXX_PMA_PMD_VS1_REMOVE_PLL_RESET 0x00
|
|
||||||
#define G6XXX_XGXS_XAUI_VS2_INPUT_MASK 0x0F /* XAUI lanes synchronized */
|
|
||||||
|
|
||||||
/* Layout of a single receive descriptor. The controller assumes that this
|
|
||||||
* structure is packed into 16 bytes, which is a safe assumption with most
|
|
||||||
* compilers. However, some compilers may insert padding between the fields,
|
|
||||||
* in which case the structure must be packed in some compiler-specific
|
|
||||||
* manner. */
|
|
||||||
struct ixgb_rx_desc {
|
|
||||||
uint64_t buff_addr;
|
|
||||||
uint16_t length;
|
|
||||||
uint16_t reserved;
|
|
||||||
uint8_t status;
|
|
||||||
uint8_t errors;
|
|
||||||
uint16_t special;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define IXGB_RX_DESC_STATUS_DD 0x01
|
|
||||||
#define IXGB_RX_DESC_STATUS_EOP 0x02
|
|
||||||
#define IXGB_RX_DESC_STATUS_IXSM 0x04
|
|
||||||
#define IXGB_RX_DESC_STATUS_VP 0x08
|
|
||||||
#define IXGB_RX_DESC_STATUS_TCPCS 0x20
|
|
||||||
#define IXGB_RX_DESC_STATUS_IPCS 0x40
|
|
||||||
#define IXGB_RX_DESC_STATUS_PIF 0x80
|
|
||||||
|
|
||||||
#define IXGB_RX_DESC_ERRORS_CE 0x01
|
|
||||||
#define IXGB_RX_DESC_ERRORS_SE 0x02
|
|
||||||
#define IXGB_RX_DESC_ERRORS_P 0x08
|
|
||||||
#define IXGB_RX_DESC_ERRORS_TCPE 0x20
|
|
||||||
#define IXGB_RX_DESC_ERRORS_IPE 0x40
|
|
||||||
#define IXGB_RX_DESC_ERRORS_RXE 0x80
|
|
||||||
|
|
||||||
#define IXGB_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
|
|
||||||
#define IXGB_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
|
|
||||||
#define IXGB_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */
|
|
||||||
|
|
||||||
/* Layout of a single transmit descriptor. The controller assumes that this
|
|
||||||
* structure is packed into 16 bytes, which is a safe assumption with most
|
|
||||||
* compilers. However, some compilers may insert padding between the fields,
|
|
||||||
* in which case the structure must be packed in some compiler-specific
|
|
||||||
* manner. */
|
|
||||||
struct ixgb_tx_desc {
|
|
||||||
uint64_t buff_addr;
|
|
||||||
uint32_t cmd_type_len;
|
|
||||||
uint8_t status;
|
|
||||||
uint8_t popts;
|
|
||||||
uint16_t vlan;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define IXGB_TX_DESC_LENGTH_MASK 0x000FFFFF
|
|
||||||
#define IXGB_TX_DESC_TYPE_MASK 0x00F00000
|
|
||||||
#define IXGB_TX_DESC_TYPE_SHIFT 20
|
|
||||||
#define IXGB_TX_DESC_CMD_MASK 0xFF000000
|
|
||||||
#define IXGB_TX_DESC_CMD_SHIFT 24
|
|
||||||
#define IXGB_TX_DESC_CMD_EOP 0x01000000
|
|
||||||
#define IXGB_TX_DESC_CMD_TSE 0x04000000
|
|
||||||
#define IXGB_TX_DESC_CMD_RS 0x08000000
|
|
||||||
#define IXGB_TX_DESC_CMD_VLE 0x40000000
|
|
||||||
#define IXGB_TX_DESC_CMD_IDE 0x80000000
|
|
||||||
|
|
||||||
#define IXGB_TX_DESC_TYPE 0x00100000
|
|
||||||
|
|
||||||
#define IXGB_TX_DESC_STATUS_DD 0x01
|
|
||||||
|
|
||||||
#define IXGB_TX_DESC_POPTS_IXSM 0x01
|
|
||||||
#define IXGB_TX_DESC_POPTS_TXSM 0x02
|
|
||||||
#define IXGB_TX_DESC_SPECIAL_PRI_SHIFT IXGB_RX_DESC_SPECIAL_PRI_SHIFT /* Priority is in upper 3 of 16 */
|
|
||||||
|
|
||||||
struct ixgb_context_desc {
|
|
||||||
uint8_t ipcss;
|
|
||||||
uint8_t ipcso;
|
|
||||||
uint16_t ipcse;
|
|
||||||
uint8_t tucss;
|
|
||||||
uint8_t tucso;
|
|
||||||
uint16_t tucse;
|
|
||||||
uint32_t cmd_type_len;
|
|
||||||
uint8_t status;
|
|
||||||
uint8_t hdr_len;
|
|
||||||
uint16_t mss;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define IXGB_CONTEXT_DESC_CMD_TCP 0x01000000
|
|
||||||
#define IXGB_CONTEXT_DESC_CMD_IP 0x02000000
|
|
||||||
#define IXGB_CONTEXT_DESC_CMD_TSE 0x04000000
|
|
||||||
#define IXGB_CONTEXT_DESC_CMD_RS 0x08000000
|
|
||||||
#define IXGB_CONTEXT_DESC_CMD_IDE 0x80000000
|
|
||||||
|
|
||||||
#define IXGB_CONTEXT_DESC_TYPE 0x00000000
|
|
||||||
|
|
||||||
#define IXGB_CONTEXT_DESC_STATUS_DD 0x01
|
|
||||||
|
|
||||||
/* Filters */
|
|
||||||
#define IXGB_RAR_ENTRIES 16 /* Number of entries in Rx Address array */
|
|
||||||
#define IXGB_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
|
|
||||||
#define IXGB_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
|
|
||||||
|
|
||||||
#define IXGB_MEMORY_REGISTER_BASE_ADDRESS 0
|
|
||||||
#define ENET_HEADER_SIZE 14
|
|
||||||
#define ENET_FCS_LENGTH 4
|
|
||||||
#define IXGB_MAX_NUM_MULTICAST_ADDRESSES 128
|
|
||||||
#define IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS 60
|
|
||||||
#define IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS 1514
|
|
||||||
#define IXGB_MAX_JUMBO_FRAME_SIZE 0x3F00
|
|
||||||
|
|
||||||
/* Phy Addresses */
|
|
||||||
#define IXGB_OPTICAL_PHY_ADDR 0x0 /* Optical Module phy address*/
|
|
||||||
#define IXGB_XAUII_PHY_ADDR 0x1 /* Xauii transceiver phy address*/
|
|
||||||
#define IXGB_DIAG_PHY_ADDR 0x1F/* Diagnostic Device phy address*/
|
|
||||||
|
|
||||||
/* This structure takes a 64k flash and maps it for identification commands */
|
|
||||||
struct ixgb_flash_buffer {
|
|
||||||
uint8_t manufacturer_id;
|
|
||||||
uint8_t device_id;
|
|
||||||
uint8_t filler1[0x2AA8];
|
|
||||||
uint8_t cmd2;
|
|
||||||
uint8_t filler2[0x2AAA];
|
|
||||||
uint8_t cmd1;
|
|
||||||
uint8_t filler3[0xAAAA];
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This is a little-endian specific check.
|
|
||||||
*/
|
|
||||||
#define IS_MULTICAST(Address) \
|
|
||||||
(boolean_t)(((uint8_t *)(Address))[0] & ((uint8_t)0x01))
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Check whether an address is broadcast.
|
|
||||||
*/
|
|
||||||
#define IS_BROADCAST(Address) \
|
|
||||||
((((uint8_t *)(Address))[0] == ((uint8_t)0xff)) && (((uint8_t *)(Address))[1] == ((uint8_t)0xff)))
|
|
||||||
|
|
||||||
/* Flow control parameters */
|
|
||||||
struct ixgb_fc {
|
|
||||||
uint32_t high_water; /* Flow Control High-water */
|
|
||||||
uint32_t low_water; /* Flow Control Low-water */
|
|
||||||
uint16_t pause_time; /* Flow Control Pause timer */
|
|
||||||
boolean_t send_xon; /* Flow control send XON */
|
|
||||||
ixgb_fc_type type; /* Type of flow control */
|
|
||||||
};
|
|
||||||
|
|
||||||
/* The historical defaults for the flow control values are given below. */
|
|
||||||
#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
|
|
||||||
#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
|
|
||||||
#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
|
|
||||||
|
|
||||||
/* Phy definitions */
|
|
||||||
#define IXGB_MAX_PHY_REG_ADDRESS 0xFFFF
|
|
||||||
#define IXGB_MAX_PHY_ADDRESS 31
|
|
||||||
#define IXGB_MAX_PHY_DEV_TYPE 31
|
|
||||||
|
|
||||||
/* Bus parameters */
|
|
||||||
struct ixgb_bus {
|
|
||||||
ixgb_bus_speed speed;
|
|
||||||
ixgb_bus_width width;
|
|
||||||
ixgb_bus_type type;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct ixgb_hw {
|
|
||||||
uint8_t *hw_addr; /* Base Address of the hardware */
|
|
||||||
void *back; /* Pointer to OS-dependent struct */
|
|
||||||
struct ixgb_fc fc; /* Flow control parameters */
|
|
||||||
struct ixgb_bus bus; /* Bus parameters */
|
|
||||||
uint32_t phy_id; /* Phy Identifier */
|
|
||||||
uint32_t phy_addr; /* XGMII address of Phy */
|
|
||||||
ixgb_mac_type mac_type; /* Identifier for MAC controller */
|
|
||||||
ixgb_phy_type phy_type; /* Transceiver/phy identifier */
|
|
||||||
uint32_t max_frame_size; /* Maximum frame size supported */
|
|
||||||
uint32_t mc_filter_type; /* Multicast filter hash type */
|
|
||||||
uint32_t num_mc_addrs; /* Number of current Multicast addrs*/
|
|
||||||
uint8_t curr_mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS]; /* Individual address currently programmed in MAC */
|
|
||||||
uint32_t num_tx_desc; /* Number of Transmit descriptors */
|
|
||||||
uint32_t num_rx_desc; /* Number of Receive descriptors */
|
|
||||||
uint32_t rx_buffer_size; /* Size of Receive buffer */
|
|
||||||
boolean_t link_up; /* TRUE if link is valid */
|
|
||||||
boolean_t adapter_stopped; /* State of adapter */
|
|
||||||
uint16_t device_id; /* device id from PCI configuration space */
|
|
||||||
uint16_t vendor_id; /* vendor id from PCI configuration space */
|
|
||||||
uint8_t revision_id; /* revision id from PCI configuration space */
|
|
||||||
uint16_t subsystem_vendor_id;/* subsystem vendor id from PCI configuration space */
|
|
||||||
uint16_t subsystem_id; /* subsystem id from PCI configuration space */
|
|
||||||
uint32_t bar0; /* Base Address registers */
|
|
||||||
uint32_t bar1;
|
|
||||||
uint32_t bar2;
|
|
||||||
uint32_t bar3;
|
|
||||||
uint16_t pci_cmd_word; /* PCI command register id from PCI configuration space */
|
|
||||||
uint16_t eeprom[IXGB_EEPROM_SIZE]; /* EEPROM contents read at init time */
|
|
||||||
unsigned long io_base; /* Our I/O mapped location */
|
|
||||||
uint32_t lastLFC;
|
|
||||||
uint32_t lastRFC;
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Statistics reported by the hardware */
|
|
||||||
struct ixgb_hw_stats {
|
|
||||||
uint64_t tprl;
|
|
||||||
uint64_t tprh;
|
|
||||||
uint64_t gprcl;
|
|
||||||
uint64_t gprch;
|
|
||||||
uint64_t bprcl;
|
|
||||||
uint64_t bprch;
|
|
||||||
uint64_t mprcl;
|
|
||||||
uint64_t mprch;
|
|
||||||
uint64_t uprcl;
|
|
||||||
uint64_t uprch;
|
|
||||||
uint64_t vprcl;
|
|
||||||
uint64_t vprch;
|
|
||||||
uint64_t jprcl;
|
|
||||||
uint64_t jprch;
|
|
||||||
uint64_t gorcl;
|
|
||||||
uint64_t gorch;
|
|
||||||
uint64_t torl;
|
|
||||||
uint64_t torh;
|
|
||||||
uint64_t rnbc;
|
|
||||||
uint64_t ruc;
|
|
||||||
uint64_t roc;
|
|
||||||
uint64_t rlec;
|
|
||||||
uint64_t crcerrs;
|
|
||||||
uint64_t icbc;
|
|
||||||
uint64_t ecbc;
|
|
||||||
uint64_t mpc;
|
|
||||||
uint64_t tptl;
|
|
||||||
uint64_t tpth;
|
|
||||||
uint64_t gptcl;
|
|
||||||
uint64_t gptch;
|
|
||||||
uint64_t bptcl;
|
|
||||||
uint64_t bptch;
|
|
||||||
uint64_t mptcl;
|
|
||||||
uint64_t mptch;
|
|
||||||
uint64_t uptcl;
|
|
||||||
uint64_t uptch;
|
|
||||||
uint64_t vptcl;
|
|
||||||
uint64_t vptch;
|
|
||||||
uint64_t jptcl;
|
|
||||||
uint64_t jptch;
|
|
||||||
uint64_t gotcl;
|
|
||||||
uint64_t gotch;
|
|
||||||
uint64_t totl;
|
|
||||||
uint64_t toth;
|
|
||||||
uint64_t dc;
|
|
||||||
uint64_t plt64c;
|
|
||||||
uint64_t tsctc;
|
|
||||||
uint64_t tsctfc;
|
|
||||||
uint64_t ibic;
|
|
||||||
uint64_t rfc;
|
|
||||||
uint64_t lfc;
|
|
||||||
uint64_t pfrc;
|
|
||||||
uint64_t pftc;
|
|
||||||
uint64_t mcfrc;
|
|
||||||
uint64_t mcftc;
|
|
||||||
uint64_t xonrxc;
|
|
||||||
uint64_t xontxc;
|
|
||||||
uint64_t xoffrxc;
|
|
||||||
uint64_t xofftxc;
|
|
||||||
uint64_t rjc;
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Function Prototypes */
|
|
||||||
extern boolean_t ixgb_adapter_stop(struct ixgb_hw *hw);
|
|
||||||
extern boolean_t ixgb_init_hw(struct ixgb_hw *hw);
|
|
||||||
extern boolean_t ixgb_adapter_start(struct ixgb_hw *hw);
|
|
||||||
extern void ixgb_init_rx_addrs(struct ixgb_hw *hw);
|
|
||||||
extern void ixgb_check_for_link(struct ixgb_hw *hw);
|
|
||||||
extern boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw);
|
|
||||||
extern boolean_t ixgb_setup_fc(struct ixgb_hw *hw);
|
|
||||||
extern void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
|
|
||||||
extern boolean_t mac_addr_valid(uint8_t *mac_addr);
|
|
||||||
|
|
||||||
extern uint16_t ixgb_read_phy_reg(struct ixgb_hw *hw,
|
|
||||||
uint32_t reg_addr,
|
|
||||||
uint32_t phy_addr,
|
|
||||||
uint32_t device_type);
|
|
||||||
|
|
||||||
extern void ixgb_write_phy_reg(struct ixgb_hw *hw,
|
|
||||||
uint32_t reg_addr,
|
|
||||||
uint32_t phy_addr,
|
|
||||||
uint32_t device_type,
|
|
||||||
uint16_t data);
|
|
||||||
|
|
||||||
extern void ixgb_rar_set(struct ixgb_hw *hw,
|
|
||||||
uint8_t *addr,
|
|
||||||
uint32_t index);
|
|
||||||
|
|
||||||
|
|
||||||
/* Filters (multicast, vlan, receive) */
|
|
||||||
extern void ixgb_mc_addr_list_update(struct ixgb_hw *hw,
|
|
||||||
uint8_t * mc_addr_list,
|
|
||||||
uint32_t mc_addr_count,
|
|
||||||
uint32_t pad);
|
|
||||||
|
|
||||||
/* Vfta functions */
|
|
||||||
extern void ixgb_write_vfta(struct ixgb_hw *hw,
|
|
||||||
uint32_t offset,
|
|
||||||
uint32_t value);
|
|
||||||
|
|
||||||
extern void ixgb_clear_vfta(struct ixgb_hw *hw);
|
|
||||||
|
|
||||||
|
|
||||||
/* Access functions to eeprom data */
|
|
||||||
void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t *mac_addr);
|
|
||||||
uint16_t ixgb_get_ee_compatibility(struct ixgb_hw *hw);
|
|
||||||
uint32_t ixgb_get_ee_pba_number(struct ixgb_hw *hw);
|
|
||||||
uint16_t ixgb_get_ee_init_ctrl_reg_1(struct ixgb_hw *hw);
|
|
||||||
uint16_t ixgb_get_ee_init_ctrl_reg_2(struct ixgb_hw *hw);
|
|
||||||
uint16_t ixgb_get_ee_subsystem_id(struct ixgb_hw *hw);
|
|
||||||
uint16_t ixgb_get_ee_subvendor_id(struct ixgb_hw *hw);
|
|
||||||
uint16_t ixgb_get_ee_device_id(struct ixgb_hw *hw);
|
|
||||||
uint16_t ixgb_get_ee_vendor_id(struct ixgb_hw *hw);
|
|
||||||
uint16_t ixgb_get_ee_swdpins_reg(struct ixgb_hw *hw);
|
|
||||||
uint8_t ixgb_get_ee_d3_power(struct ixgb_hw *hw);
|
|
||||||
uint8_t ixgb_get_ee_d0_power(struct ixgb_hw *hw);
|
|
||||||
boolean_t ixgb_get_eeprom_data(struct ixgb_hw *hw);
|
|
||||||
uint16_t ixgb_get_eeprom_word(struct ixgb_hw *hw, uint16_t index);
|
|
||||||
|
|
||||||
/* Everything else */
|
|
||||||
void ixgb_led_on(struct ixgb_hw *hw);
|
|
||||||
void ixgb_led_off(struct ixgb_hw *hw);
|
|
||||||
void ixgb_write_pci_cfg(struct ixgb_hw *hw,
|
|
||||||
uint32_t reg,
|
|
||||||
uint16_t * value);
|
|
||||||
|
|
||||||
|
|
||||||
#endif /* _IXGB_HW_H_ */
|
|
||||||
@ -1,58 +0,0 @@
|
|||||||
/*******************************************************************************
|
|
||||||
SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
|
|
||||||
Copyright (c) 2001-2004, Intel Corporation
|
|
||||||
All rights reserved.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without
|
|
||||||
modification, are permitted provided that the following conditions are met:
|
|
||||||
|
|
||||||
1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
this list of conditions and the following disclaimer.
|
|
||||||
|
|
||||||
2. Redistributions in binary form must reproduce the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer in the
|
|
||||||
documentation and/or other materials provided with the distribution.
|
|
||||||
|
|
||||||
3. Neither the name of the Intel Corporation nor the names of its
|
|
||||||
contributors may be used to endorse or promote products derived from
|
|
||||||
this software without specific prior written permission.
|
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
|
|
||||||
*******************************************************************************/
|
|
||||||
|
|
||||||
/*$FreeBSD$*/
|
|
||||||
|
|
||||||
#ifndef _IXGB_IDS_H_
|
|
||||||
#define _IXGB_IDS_H_
|
|
||||||
|
|
||||||
/**********************************************************************
|
|
||||||
** The Device IDs for 10 Gigabit MACs
|
|
||||||
**********************************************************************/
|
|
||||||
|
|
||||||
#define IXGB_DEVICE_ID_82597EX 0x1048 /* Cibolo A1, -LR (1310nm) */
|
|
||||||
#define IXGB_DEVICE_ID_82597EX_SR 0x1A48 /* Cibolo B0, -SR (850nm) */
|
|
||||||
|
|
||||||
#define IXGB_SUBDEVICE_ID_A11F 0xA11F /* Adapter-OEM-1310nm-Fiber */
|
|
||||||
#define IXGB_SUBDEVICE_ID_A01F 0xA01F /* Adapter-Retail-1310nm-Fiber */
|
|
||||||
|
|
||||||
#define IXGB_SUBDEVICE_ID_A15F 0xA15F /* Adapter-OEM-850nm-Fiber */
|
|
||||||
#define IXGB_SUBDEVICE_ID_A05F 0xA05F /* Adapter-Retail-850nm-Fiber */
|
|
||||||
|
|
||||||
#define IXGB_SUBDEVICE_ID_A12F 0xA12F /* Adapter-OEM-1310nm-Fiber */
|
|
||||||
#define IXGB_SUBDEVICE_ID_A02F 0xA02F /* Adapter-Retail-1310nm-Fiber */
|
|
||||||
|
|
||||||
#endif /* #ifndef _IXGB_IDS_H_ */
|
|
||||||
|
|
||||||
/* End of File */
|
|
||||||
@ -230,7 +230,6 @@ device puc # Multi I/O cards and multi-channel UARTs
|
|||||||
device bxe # Broadcom NetXtreme II BCM5771X/BCM578XX 10GbE
|
device bxe # Broadcom NetXtreme II BCM5771X/BCM578XX 10GbE
|
||||||
device de # DEC/Intel DC21x4x (``Tulip'')
|
device de # DEC/Intel DC21x4x (``Tulip'')
|
||||||
device em # Intel PRO/1000 Gigabit Ethernet Family
|
device em # Intel PRO/1000 Gigabit Ethernet Family
|
||||||
device ixgb # Intel PRO/10GbE Ethernet Card
|
|
||||||
device le # AMD Am7900 LANCE and Am79C9xx PCnet
|
device le # AMD Am7900 LANCE and Am79C9xx PCnet
|
||||||
device ti # Alteon Networks Tigon I/II gigabit Ethernet
|
device ti # Alteon Networks Tigon I/II gigabit Ethernet
|
||||||
device txp # 3Com 3cR990 (``Typhoon'')
|
device txp # 3Com 3cR990 (``Typhoon'')
|
||||||
|
|||||||
@ -203,7 +203,6 @@ SUBDIR= \
|
|||||||
${_iwnfw} \
|
${_iwnfw} \
|
||||||
${_ix} \
|
${_ix} \
|
||||||
${_ixv} \
|
${_ixv} \
|
||||||
${_ixgb} \
|
|
||||||
${_ixl} \
|
${_ixl} \
|
||||||
${_ixlv} \
|
${_ixlv} \
|
||||||
jme \
|
jme \
|
||||||
@ -666,7 +665,6 @@ _ipw= ipw
|
|||||||
_iwi= iwi
|
_iwi= iwi
|
||||||
_iwm= iwm
|
_iwm= iwm
|
||||||
_iwn= iwn
|
_iwn= iwn
|
||||||
_ixgb= ixgb
|
|
||||||
.if ${MK_SOURCELESS_UCODE} != "no"
|
.if ${MK_SOURCELESS_UCODE} != "no"
|
||||||
_ipwfw= ipwfw
|
_ipwfw= ipwfw
|
||||||
_iwifw= iwifw
|
_iwifw= iwifw
|
||||||
|
|||||||
@ -1,9 +0,0 @@
|
|||||||
#$FreeBSD$
|
|
||||||
|
|
||||||
.PATH: ${SRCTOP}/sys/dev/ixgb
|
|
||||||
|
|
||||||
KMOD= if_ixgb
|
|
||||||
SRCS= if_ixgb.c ixgb_hw.c ixgb_ee.c
|
|
||||||
SRCS+= device_if.h bus_if.h pci_if.h
|
|
||||||
|
|
||||||
.include <bsd.kmod.mk>
|
|
||||||
@ -5727,8 +5727,7 @@ pf_route6(struct mbuf **m, struct pf_rule *r, int dir, struct ifnet *oifp,
|
|||||||
|
|
||||||
/*
|
/*
|
||||||
* FreeBSD supports cksum offloads for the following drivers.
|
* FreeBSD supports cksum offloads for the following drivers.
|
||||||
* em(4), fxp(4), ixgb(4), lge(4), ndis(4), nge(4), re(4),
|
* em(4), fxp(4), lge(4), ndis(4), nge(4), re(4), ti(4), txp(4), xl(4)
|
||||||
* ti(4), txp(4), xl(4)
|
|
||||||
*
|
*
|
||||||
* CSUM_DATA_VALID | CSUM_PSEUDO_HDR :
|
* CSUM_DATA_VALID | CSUM_PSEUDO_HDR :
|
||||||
* network driver performed cksum including pseudo header, need to verify
|
* network driver performed cksum including pseudo header, need to verify
|
||||||
|
|||||||
@ -177,7 +177,6 @@ device uart # Multi-uart driver
|
|||||||
# PCI Ethernet NICs.
|
# PCI Ethernet NICs.
|
||||||
#device de # DEC/Intel DC21x4x (``Tulip'')
|
#device de # DEC/Intel DC21x4x (``Tulip'')
|
||||||
device em # Intel PRO/1000 adapter Gigabit Ethernet Card
|
device em # Intel PRO/1000 adapter Gigabit Ethernet Card
|
||||||
#device ixgb # Intel PRO/10GbE Ethernet Card
|
|
||||||
device le # AMD Am7900 LANCE and Am79C9xx PCnet
|
device le # AMD Am7900 LANCE and Am79C9xx PCnet
|
||||||
device ti # Alteon Networks Tigon I/II gigabit Ethernet
|
device ti # Alteon Networks Tigon I/II gigabit Ethernet
|
||||||
device txp # 3Com 3cR990 (``Typhoon'')
|
device txp # 3Com 3cR990 (``Typhoon'')
|
||||||
|
|||||||
@ -1,21 +0,0 @@
|
|||||||
# Doxyfile 1.5.2
|
|
||||||
|
|
||||||
# $FreeBSD$
|
|
||||||
|
|
||||||
#---------------------------------------------------------------------------
|
|
||||||
# Project related configuration options
|
|
||||||
#---------------------------------------------------------------------------
|
|
||||||
PROJECT_NAME = "FreeBSD kernel IXGB device code"
|
|
||||||
OUTPUT_DIRECTORY = $(DOXYGEN_DEST_PATH)/dev_ixgb/
|
|
||||||
EXTRACT_ALL = YES # for undocumented src, no warnings enabled
|
|
||||||
#---------------------------------------------------------------------------
|
|
||||||
# configuration options related to the input files
|
|
||||||
#---------------------------------------------------------------------------
|
|
||||||
INPUT = $(DOXYGEN_SRC_PATH)/dev/ixgb/ \
|
|
||||||
$(NOTREVIEWED)
|
|
||||||
|
|
||||||
GENERATE_TAGFILE = dev_ixgb/dev_ixgb.tag
|
|
||||||
|
|
||||||
@INCLUDE_PATH = $(DOXYGEN_INCLUDE_PATH)
|
|
||||||
@INCLUDE = common-Doxyfile
|
|
||||||
|
|
||||||
@ -80,7 +80,6 @@ device sio # 8250, 16[45]50 based serial ports
|
|||||||
# PCI Ethernet NICs.
|
# PCI Ethernet NICs.
|
||||||
device de # DEC/Intel DC21x4x (``Tulip'')
|
device de # DEC/Intel DC21x4x (``Tulip'')
|
||||||
device em # Intel PRO/1000 adapter Gigabit Ethernet Card
|
device em # Intel PRO/1000 adapter Gigabit Ethernet Card
|
||||||
device ixgb # Intel PRO/10GbE Ethernet Card
|
|
||||||
device txp # 3Com 3cR990 (``Typhoon'')
|
device txp # 3Com 3cR990 (``Typhoon'')
|
||||||
device vx # 3Com 3c590, 3c595 (``Vortex'')
|
device vx # 3Com 3c590, 3c595 (``Vortex'')
|
||||||
|
|
||||||
|
|||||||
@ -90,7 +90,6 @@ device sio # 8250, 16[45]50 based serial ports
|
|||||||
# PCI Ethernet NICs.
|
# PCI Ethernet NICs.
|
||||||
device de # DEC/Intel DC21x4x (``Tulip'')
|
device de # DEC/Intel DC21x4x (``Tulip'')
|
||||||
device em # Intel PRO/1000 adapter Gigabit Ethernet Card
|
device em # Intel PRO/1000 adapter Gigabit Ethernet Card
|
||||||
device ixgb # Intel PRO/10GbE Ethernet Card
|
|
||||||
device txp # 3Com 3cR990 (``Typhoon'')
|
device txp # 3Com 3cR990 (``Typhoon'')
|
||||||
device vx # 3Com 3c590, 3c595 (``Vortex'')
|
device vx # 3Com 3c590, 3c595 (``Vortex'')
|
||||||
|
|
||||||
|
|||||||
@ -79,7 +79,6 @@ device sio # 8250, 16[45]50 based serial ports
|
|||||||
# PCI Ethernet NICs.
|
# PCI Ethernet NICs.
|
||||||
device de # DEC/Intel DC21x4x (``Tulip'')
|
device de # DEC/Intel DC21x4x (``Tulip'')
|
||||||
device em # Intel PRO/1000 adapter Gigabit Ethernet Card
|
device em # Intel PRO/1000 adapter Gigabit Ethernet Card
|
||||||
device ixgb # Intel PRO/10GbE Ethernet Card
|
|
||||||
device txp # 3Com 3cR990 (``Typhoon'')
|
device txp # 3Com 3cR990 (``Typhoon'')
|
||||||
device vx # 3Com 3c590, 3c595 (``Vortex'')
|
device vx # 3Com 3c590, 3c595 (``Vortex'')
|
||||||
|
|
||||||
|
|||||||
@ -80,7 +80,6 @@ device sio # 8250, 16[45]50 based serial ports
|
|||||||
# PCI Ethernet NICs.
|
# PCI Ethernet NICs.
|
||||||
device de # DEC/Intel DC21x4x (``Tulip'')
|
device de # DEC/Intel DC21x4x (``Tulip'')
|
||||||
device em # Intel PRO/1000 adapter Gigabit Ethernet Card
|
device em # Intel PRO/1000 adapter Gigabit Ethernet Card
|
||||||
device ixgb # Intel PRO/10GbE Ethernet Card
|
|
||||||
device txp # 3Com 3cR990 (``Typhoon'')
|
device txp # 3Com 3cR990 (``Typhoon'')
|
||||||
device vx # 3Com 3c590, 3c595 (``Vortex'')
|
device vx # 3Com 3c590, 3c595 (``Vortex'')
|
||||||
|
|
||||||
|
|||||||
@ -80,7 +80,6 @@ device sio # 8250, 16[45]50 based serial ports
|
|||||||
# PCI Ethernet NICs.
|
# PCI Ethernet NICs.
|
||||||
#device de # DEC/Intel DC21x4x (``Tulip'')
|
#device de # DEC/Intel DC21x4x (``Tulip'')
|
||||||
#device em # Intel PRO/1000 adapter Gigabit Ethernet Card
|
#device em # Intel PRO/1000 adapter Gigabit Ethernet Card
|
||||||
#device ixgb # Intel PRO/10GbE Ethernet Card
|
|
||||||
#device txp # 3Com 3cR990 (``Typhoon'')
|
#device txp # 3Com 3cR990 (``Typhoon'')
|
||||||
#device vx # 3Com 3c590, 3c595 (``Vortex'')
|
#device vx # 3Com 3c590, 3c595 (``Vortex'')
|
||||||
|
|
||||||
|
|||||||
@ -48,7 +48,6 @@ device sio # 8250, 16[45]50 based serial ports
|
|||||||
# PCI Ethernet NICs.
|
# PCI Ethernet NICs.
|
||||||
device de # DEC/Intel DC21x4x (``Tulip'')
|
device de # DEC/Intel DC21x4x (``Tulip'')
|
||||||
device em # Intel PRO/1000 adapter Gigabit Ethernet Card
|
device em # Intel PRO/1000 adapter Gigabit Ethernet Card
|
||||||
device ixgb # Intel PRO/10GbE Ethernet Card
|
|
||||||
device txp # 3Com 3cR990 (``Typhoon'')
|
device txp # 3Com 3cR990 (``Typhoon'')
|
||||||
device vx # 3Com 3c590, 3c595 (``Vortex'')
|
device vx # 3Com 3c590, 3c595 (``Vortex'')
|
||||||
|
|
||||||
|
|||||||
@ -1321,7 +1321,6 @@ f_network "ipw%d" "Intel PRO/Wireless 2100 IEEE 802.11 adapter"
|
|||||||
f_network "iwi%d" "Intel PRO/Wireless 2200BG/2225BG/2915ABG adapter"
|
f_network "iwi%d" "Intel PRO/Wireless 2200BG/2225BG/2915ABG adapter"
|
||||||
f_network "iwn%d" "Intel Wireless WiFi Link 4965AGN IEEE 802.11n adapter"
|
f_network "iwn%d" "Intel Wireless WiFi Link 4965AGN IEEE 802.11n adapter"
|
||||||
f_network "ix%d" "Intel Etherexpress Ethernet card"
|
f_network "ix%d" "Intel Etherexpress Ethernet card"
|
||||||
f_network "ixgb%d" "Intel(R) PRO/10Gb Ethernet card"
|
|
||||||
f_network "ixgbe%d" "Intel(R) PRO/10Gb Ethernet card"
|
f_network "ixgbe%d" "Intel(R) PRO/10Gb Ethernet card"
|
||||||
f_network "jme%d" "JMicron JMC250 Gigabit/JMC260 Fast Ethernet"
|
f_network "jme%d" "JMicron JMC250 Gigabit/JMC260 Fast Ethernet"
|
||||||
f_network "kue%d" "Kawasaki LSI USB Ethernet adapter"
|
f_network "kue%d" "Kawasaki LSI USB Ethernet adapter"
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user