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Merge commit d7be3eab5 from llvm git (by Luís Marques):

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[RISCV] Handle fcopysign(f32, f64) and fcopysign(f64, f32)

  Summary: Adds tablegen patterns to explicitly handle fcopysign where
  the magnitude and sign arguments have different types, due to the
  sign value casts being removed the by DAGCombiner. Support for RV32IF
  follows in a separate commit. Adds tests for all relevant scenarios
  except RV32IF.

  Reviewers: lenary
  Reviewed By: lenary
  Tags: #llvm
  Differential Revision: https://reviews.llvm.org/D70678

This is a prerequisite for building and linking hard- and soft-float
riscv worlds with clang and lld.

Requested by:	jhb
MFC after:	1 week
X-MFC-With:	r353358
This commit is contained in:
Dimitry Andric 2020-01-03 20:28:06 +00:00
parent 96d5330da8
commit 2b2a17f472
1 changed files with 3 additions and 0 deletions
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3
contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
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@ -231,6 +231,9 @@ def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>;
def : PatFpr64Fpr64<fcopysign, FSGNJ_D>;
def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>;
def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2))>;
def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2,
0b111))>;
// fmadd: rs1 * rs2 + rs3
def : Pat<(fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),