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Relax TX draining in ns8250_bus_transmit().

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Since TX interrupt is generated when THRE is set, wait for TEMT set means
wait for full character transmission time.  At low speeds that may take
awhile, burning CPU time while holding sc_hwmtx lock, also congested.

This is partial revert of r317659.

PR:		240121
MFC after:	2 weeks
This commit is contained in:
Alexander Motin 2019-09-15 23:56:39 +00:00
parent eb1c42c1f0
commit 3a97344265
1 changed files with 2 additions and 7 deletions
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9
sys/dev/uart/uart_dev_ns8250.c
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@ -1029,13 +1029,8 @@ ns8250_bus_transmit(struct uart_softc *sc)
bas = &sc->sc_bas;
uart_lock(sc->sc_hwmtx);
if (sc->sc_txdatasz > 1) {
if ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0)
ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
} else {
while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
DELAY(4);
}
while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
DELAY(4);
for (i = 0; i < sc->sc_txdatasz; i++) {
uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
uart_barrier(bas);