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Add minimum cache line sizes to struct cpuinfo, use them in the new cache

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maintenance routines.  Also add a routine to invalidate the branch cache.

Submitted by:	Michal Meloun
This commit is contained in:
ian 2015-03-09 14:46:10 +00:00
parent c78382ce59
commit 3da704e7e6
4 changed files with 49 additions and 8 deletions
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15
sys/arm/arm/cpuinfo.c
View File

@ -34,7 +34,14 @@ __FBSDID("$FreeBSD$");
#include <machine/cpuinfo.h>
#include <machine/cpu-v6.h>
struct cpuinfo cpuinfo;
struct cpuinfo cpuinfo =
{
/* Use safe defaults for start */
.dcache_line_size = 32,
.dcache_line_mask = 31,
.icache_line_size = 32,
.icache_line_mask = 31,
};
/* Read and parse CPU id scheme */
void
@ -122,4 +129,10 @@ cpuinfo_init(void)
cpuinfo.generic_timer_ext = (cpuinfo.id_pfr1 >> 16) & 0xF;
cpuinfo.virtualization_ext = (cpuinfo.id_pfr1 >> 12) & 0xF;
cpuinfo.security_ext = (cpuinfo.id_pfr1 >> 4) & 0xF;
/* L1 Cache sizes */
cpuinfo.dcache_line_size = 1 << (CPU_CT_DMINLINE(cpuinfo.ctr ) + 2);
cpuinfo.dcache_line_mask = cpuinfo.dcache_line_size - 1;
cpuinfo.icache_line_size= 1 << (CPU_CT_IMINLINE(cpuinfo.ctr ) + 2);
cpuinfo.icache_line_mask = cpuinfo.icache_line_size - 1;
}

6
sys/arm/arm/genassym.c
View File

@ -45,6 +45,7 @@ __FBSDID("$FreeBSD$");
#include <machine/cpu.h>
#include <machine/proc.h>
#include <machine/cpufunc.h>
#include <machine/cpuinfo.h>
#include <machine/pte.h>
#include <machine/intr.h>
#include <machine/sysarch.h>
@ -146,3 +147,8 @@ ASSYM(MAXCOMLEN, MAXCOMLEN);
ASSYM(MAXCPU, MAXCPU);
ASSYM(NIRQ, NIRQ);
ASSYM(PCPU_SIZE, sizeof(struct pcpu));
ASSYM(DCACHE_LINE_SIZE, offsetof(struct cpuinfo, dcache_line_size));
ASSYM(DCACHE_LINE_MASK, offsetof(struct cpuinfo, dcache_line_mask));
ASSYM(ICACHE_LINE_SIZE, offsetof(struct cpuinfo, icache_line_size));
ASSYM(ICACHE_LINE_MASK, offsetof(struct cpuinfo, icache_line_mask));

30
sys/arm/include/cpu-v6.h
View File

@ -37,6 +37,9 @@
#define CPU_ASID_KERNEL 0
vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t);
vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t);
/*
* Macros to generate CP15 (system control processor) read/write functions.
*/
@ -302,7 +305,7 @@ icache_sync(vm_offset_t sva, vm_size_t size)
vm_offset_t eva = sva + size;
dsb();
for (va = sva; va < eva; va += arm_dcache_align) {
for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
#if __ARM_ARCH >= 7 && defined SMP
_CP15_DCCMVAU(va);
#else
@ -332,6 +335,19 @@ icache_inv_all(void)
isb();
}
/* Invalidate branch predictor buffer */
static __inline void
bpb_inv_all(void)
{
#if __ARM_ARCH >= 7 && defined SMP
_CP15_BPIALLIS();
#else
_CP15_BPIALL();
#endif
dsb();
isb();
}
/* Write back D-cache to PoU */
static __inline void
dcache_wb_pou(vm_offset_t sva, vm_size_t size)
@ -340,7 +356,7 @@ dcache_wb_pou(vm_offset_t sva, vm_size_t size)
vm_offset_t eva = sva + size;
dsb();
for (va = sva; va < eva; va += arm_dcache_align) {
for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
#if __ARM_ARCH >= 7 && defined SMP
_CP15_DCCMVAU(va);
#else
@ -358,7 +374,7 @@ dcache_inv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
vm_offset_t eva = sva + size;
/* invalidate L1 first */
for (va = sva; va < eva; va += arm_dcache_align) {
for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
_CP15_DCIMVAC(va);
}
dsb();
@ -368,7 +384,7 @@ dcache_inv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
dsb();
/* then L1 again */
for (va = sva; va < eva; va += arm_dcache_align) {
for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
_CP15_DCIMVAC(va);
}
dsb();
@ -383,7 +399,7 @@ dcache_wb_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
dsb();
for (va = sva; va < eva; va += arm_dcache_align) {
for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
_CP15_DCCMVAC(va);
}
dsb();
@ -401,7 +417,7 @@ dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
dsb();
/* write back L1 first */
for (va = sva; va < eva; va += arm_dcache_align) {
for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
_CP15_DCCMVAC(va);
}
dsb();
@ -410,7 +426,7 @@ dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
cpu_l2cache_wbinv_range(pa, size);
/* then invalidate L1 */
for (va = sva; va < eva; va += arm_dcache_align) {
for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
_CP15_DCIMVAC(va);
}
dsb();

6
sys/arm/include/cpuinfo.h
View File

@ -82,6 +82,12 @@ struct cpuinfo {
int generic_timer_ext;
int virtualization_ext;
int security_ext;
/* L1 cache info */
int dcache_line_size;
int dcache_line_mask;
int icache_line_size;
int icache_line_mask;
};
extern struct cpuinfo cpuinfo;