Flesh out some initial EDMA TX FIFO fill, complete and refill routines.
Note: This is totally sub-optimal and a work in progress. * Support filling an empty FIFO TXQ with frames from the ath_buf queue in the ath_txq list. However, since there's (currently) no clean, easy way to separate the frames that are in the FIFO versus just waiting, the code waits for the FIFO to be totally empty before it attempts to queue more. This is highly sub-optimal but is enough to get the ball rolling. * A _lot_ of the code assumes that the TX status is filled out in the struct ath_buf bf_status field. So for now, memcpy() the completion over. * None of the TX drain / reset routines will attempt to complete completed frames before draining, so it can't be used for 802.11n TX aggregation. (This won't work anyway, as the aggregation TX descriptor API hasn't yet been converted; and that'll happen in some future commits.) * Fix an issue where the FIFO counter wasn't being incremented, leading to the queue logic just plain not working. * HAL_EIO means "descriptor wasn't valid", versus "not finished, don't continue." So don't stop processing descriptors when HAL_EIO is hit. * Don't service frame completion from the beacon queue. It isn't currently fully setup like a real queue and the first attempt at accessing the queue lock will panic the kernel. Tested: * AR9380, STA mode This commit is brought to you by said AR9380 in STA mode.
This commit is contained in:
Adrian Chadd
parent
42083b3d66
commit
4aa8818b55
@ -130,6 +130,24 @@ __FBSDID("$FreeBSD$");
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MALLOC_DECLARE(M_ATHDEV);
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static void
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ath_edma_tx_fifo_fill(struct ath_softc *sc, struct ath_txq *txq)
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{
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struct ath_buf *bf;
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ATH_TXQ_LOCK_ASSERT(txq);
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DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: called\n", __func__);
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TAILQ_FOREACH(bf, &txq->axq_q, bf_list) {
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if (txq->axq_fifo_depth >= HAL_TXFIFO_DEPTH)
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break;
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ath_hal_puttxbuf(sc->sc_ah, txq->axq_qnum, bf->bf_daddr);
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txq->axq_fifo_depth++;
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}
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ath_hal_txstart(sc->sc_ah, txq->axq_qnum);
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}
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/*
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* Re-initialise the DMA FIFO with the current contents of
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* said TXQ.
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@ -149,6 +167,10 @@ ath_edma_dma_restart(struct ath_softc *sc, struct ath_txq *txq)
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__func__,
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txq,
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txq->axq_qnum);
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ATH_TXQ_LOCK_ASSERT(txq);
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ath_edma_tx_fifo_fill(sc, txq);
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}
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/*
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@ -186,9 +208,15 @@ ath_edma_xmit_handoff_hw(struct ath_softc *sc, struct ath_txq *txq,
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/* Push and update frame stats */
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ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
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#ifdef ATH_DEBUG
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if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
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ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 0);
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#endif /* ATH_DEBUG */
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/* Only schedule to the FIFO if there's space */
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if (txq->axq_fifo_depth < HAL_TXFIFO_DEPTH) {
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ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
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txq->axq_fifo_depth++;
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ath_hal_txstart(ah, txq->axq_qnum);
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}
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}
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@ -259,7 +287,8 @@ ath_edma_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq,
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ATH_TXQ_LOCK_ASSERT(txq);
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device_printf(sc->sc_dev, "%s: called; bf=%p, txq=%p, qnum=%d\n",
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DPRINTF(sc, ATH_DEBUG_XMIT_DESC,
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"%s: called; bf=%p, txq=%p, qnum=%d\n",
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__func__,
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bf,
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txq,
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@ -355,8 +384,34 @@ ath_edma_dma_txteardown(struct ath_softc *sc)
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static void
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ath_edma_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type)
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{
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struct ifnet *ifp = sc->sc_ifp;
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int i;
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device_printf(sc->sc_dev, "%s: called\n", __func__);
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(void) ath_stoptxdma(sc);
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/*
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* If reset type is noloss, the TX FIFO needs to be serviced
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* and those frames need to be handled.
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*
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* Otherwise, just toss everything in each TX queue.
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*/
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/* XXX dump out the TX completion FIFO contents */
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/* XXX dump out the frames */
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/* XXX for now, just drain */
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for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
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if (ATH_TXQ_SETUP(sc, i))
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ath_tx_draintxq(sc, &sc->sc_txq[i]);
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}
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IF_LOCK(&ifp->if_snd);
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ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
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IF_UNLOCK(&ifp->if_snd);
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sc->sc_wd_timer = 0;
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}
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/*
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@ -370,18 +425,35 @@ ath_edma_tx_proc(void *arg, int npending)
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HAL_STATUS status;
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struct ath_tx_status ts;
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struct ath_txq *txq;
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struct ath_buf *bf;
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struct ieee80211_node *ni;
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int nacked;
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device_printf(sc->sc_dev, "%s: called, npending=%d\n",
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DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: called, npending=%d\n",
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__func__, npending);
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for (;;) {
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bzero(&ts, sizeof(ts));
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ATH_TXSTATUS_LOCK(sc);
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status = ath_hal_txprocdesc(ah, NULL, (void *) &ts);
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ATH_TXSTATUS_UNLOCK(sc);
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if (status != HAL_OK)
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if (status == HAL_EINPROGRESS)
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break;
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/*
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* If there is an error with this descriptor, continue
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* processing.
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*
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* XXX TBD: log some statistics?
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*/
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if (status == HAL_EIO) {
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device_printf(sc->sc_dev, "%s: invalid TX status?\n",
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__func__);
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continue;
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}
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/*
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* At this point we have a valid status descriptor.
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* The QID and descriptor ID (which currently isn't set)
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@ -391,12 +463,129 @@ ath_edma_tx_proc(void *arg, int npending)
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* -head- of the given QID. Eventually we should verify
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* this by using the descriptor ID.
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*/
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device_printf(sc->sc_dev, "%s: qcuid=%d\n",
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__func__,
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ts.ts_queue_id);
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/*
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* The beacon queue is not currently a "real" queue.
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* Frames aren't pushed onto it and the lock isn't setup.
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* So skip it for now; the beacon handling code will
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* free and alloc more beacon buffers as appropriate.
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*/
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if (ts.ts_queue_id == sc->sc_bhalq)
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continue;
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txq = &sc->sc_txq[ts.ts_queue_id];
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ATH_TXQ_LOCK(txq);
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bf = TAILQ_FIRST(&txq->axq_q);
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DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: qcuid=%d, bf=%p\n",
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__func__,
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ts.ts_queue_id, bf);
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#if 0
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/* XXX assert the buffer/descriptor matches the status descid */
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if (ts.ts_desc_id != bf->bf_descid) {
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device_printf(sc->sc_dev,
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"%s: mismatched descid (qid=%d, tsdescid=%d, "
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"bfdescid=%d\n",
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__func__,
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ts.ts_queue_id,
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ts.ts_desc_id,
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bf->bf_descid);
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}
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#endif
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/* This removes the buffer and decrements the queue depth */
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ATH_TXQ_REMOVE(txq, bf, bf_list);
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if (bf->bf_state.bfs_aggr)
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txq->axq_aggr_depth--;
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txq->axq_fifo_depth --;
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/* XXX assert FIFO depth >= 0 */
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ATH_TXQ_UNLOCK(txq);
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/*
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* First we need to make sure ts_rate is valid.
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*
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* Pre-EDMA chips pass the whole TX descriptor to
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* the proctxdesc function which will then fill out
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* ts_rate based on the ts_finaltsi (final TX index)
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* in the TX descriptor. However the TX completion
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* FIFO doesn't have this information. So here we
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* do a separate HAL call to populate that information.
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*/
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/* XXX TODO */
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/* XXX faked for now. Ew. */
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if (ts.ts_finaltsi < 4) {
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ts.ts_rate =
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bf->bf_state.bfs_rc[ts.ts_finaltsi].ratecode;
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} else {
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device_printf(sc->sc_dev, "%s: finaltsi=%d\n",
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__func__,
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ts.ts_finaltsi);
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ts.ts_rate = bf->bf_state.bfs_rc[0].ratecode;
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}
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/*
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* XXX This is terrible.
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*
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* Right now, some code uses the TX status that is
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* passed in here, but the completion handlers in the
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* software TX path also use bf_status.ds_txstat.
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* Ew. That should all go away.
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*
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* XXX It's also possible the rate control completion
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* routine is called twice.
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*/
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memcpy(&bf->bf_status, &ts, sizeof(ts));
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ni = bf->bf_node;
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/* Update RSSI */
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/* XXX duplicate from ath_tx_processq */
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if (ni != NULL && ts.ts_status == 0 &&
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((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) {
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nacked++;
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sc->sc_stats.ast_tx_rssi = ts.ts_rssi;
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ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
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ts.ts_rssi);
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}
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/* Handle frame completion and rate control update */
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ath_tx_process_buf_completion(sc, txq, &ts, bf);
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/* bf is invalid at this point */
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/*
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* Now that there's space in the FIFO, let's push some
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* more frames into it.
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*
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* Unfortunately for now, the txq has FIFO and non-FIFO
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* frames in the same linked list, so there's no way
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* to quickly/easily populate frames without walking
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* the queue and skipping 'axq_fifo_depth' frames.
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*
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* So for now, let's only repopulate the FIFO once it
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* is empty. It's sucky for performance but it's enough
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* to begin validating that things are somewhat
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* working.
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*/
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ATH_TXQ_LOCK(txq);
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if (txq->axq_fifo_depth == 0) {
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ath_edma_tx_fifo_fill(sc, txq);
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}
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ATH_TXQ_UNLOCK(txq);
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}
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sc->sc_wd_timer = 0;
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/* Kick software scheduler */
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/*
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* XXX It's inefficient to do this if the FIFO queue is full,
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* but there's no easy way right now to only populate
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* the txq task for _one_ TXQ. This should be fixed.
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*/
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taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask);
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}
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static void
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