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Fix the long standing problem with poor transferrates on Intel ICHH type

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chips. The DMA timing value was set on device 0 for all devices :/

Prodded by: Harald Schmalzbauer
This commit is contained in:
sos 2005-06-09 21:13:44 +00:00
parent 036c7990fa
commit 4fa0803f24
1 changed files with 3 additions and 2 deletions
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5
sys/dev/ata/ata-chipset.c
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@ -1740,8 +1740,9 @@ ata_intel_new_setmode(device_t dev, int mode)
if (mode >= ATA_UDMA0) {
pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno<<2))) |
(0x01 + !(mode & 0x01)), 2);
pci_write_config(gparent, 0x4a,
(reg4a & ~(0x3 << (devno << 2))) |
((0x01 + !(mode & 0x01)) << (devno << 2)), 2);
}
else {
pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);