Add a memory barrier to ensure the atomic write is visible to the other

CPUs before waking them up.

Sponsored by:	DARPA, AFRL

sys/arm64/arm64/mp_machdep.c

@@ -236,7 +236,10 @@ release_aps(void *dummy __unused)
 
 	atomic_store_rel_int(&aps_ready, 1);
 	/* Wake up the other CPUs */
-	__asm __volatile("sev");
+	__asm __volatile(
+	    "dsb ishst	\n"
+	    "sev	\n"
+	    ::: "memory");
 
 	printf("Release APs\n");