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- The payload of Write Request Quad and Read Response Quad must be

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network byte order.
- Set ATRetries register after each bus reset because the value is 'undef'
	in OHCI spec.
This commit is contained in:
simokawa 2003-03-24 04:06:21 +00:00
parent 176bfd0826
commit 5a06ca07d7
2 changed files with 9 additions and 2 deletions
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2
sys/dev/firewire/fwmem.c
View File

@ -163,7 +163,7 @@ fwmem_write_quad(
fp->mode.wreqq.dest_hi = htons(dst_hi);
fp->mode.wreqq.dest_lo = htonl(dst_lo);
fp->mode.wreqq.data = htonl(data);
fp->mode.wreqq.data = data;
if (fwmem_debug)
printf("fwmem_write_quad: %d %04x:%08x %08x\n", fwdev->dst,

9
sys/dev/firewire/fwohci.c
View File

@ -169,6 +169,7 @@ void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *));
#define NDVDB (DVBUF * NDB)
#define OHCI_VERSION 0x00
#define OHCI_ATRETRY 0x08
#define OHCI_CROMHDR 0x18
#define OHCI_BUS_OPT 0x20
#define OHCI_BUSIRMC (1 << 31)
@ -810,6 +811,10 @@ txloop:
for( i = 0 ; i < hdr_off ; i+= 4){
ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]);
}
/* XXX payload must be network byte order */
if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) {
ohcifp->mode.ld[3] = htonl(ohcifp->mode.ld[3]);
}
ohcifp->mode.common.spd = xfer->spd;
if (tcode == FWTCODE_STREAM ){
hdr_len = 8;
@ -1882,6 +1887,8 @@ busresetout:
OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
OWRITE(sc, OHCI_PREQLO, 0xffffffff);
OWRITE(sc, OHCI_PREQUPPER, 0x10000);
/* Set ATRetries register */
OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
/*
** Checking whether the node is root or not. If root, turn on
** cycle master.
@ -2795,7 +2802,7 @@ fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
switch(stat){
case FWOHCIEV_ACKPEND:
#if 0
printf("fwohci_arcv: ack pending..\n");
printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode);
#endif
/* fall through */
case FWOHCIEV_ACKCOMPL: