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Correct the CONFIG0_VI value. According to

Browse Source 
http://www.t-es-t.hu/download/mips/md00090c.pdf this is bit 3 of the
config0 word, not bit 2.  This should fix virtually indexed caches
(relatively new in the MIPS world, so no current platforms used this
and current code just uses it as an optimization). It was causing
false positives on newer platforms that default to large values for
the kseg0 cache coherency attribute.

Submitted by: Stanislav Galabov
PR:	205249
This commit is contained in:
imp 2015-12-11 16:51:04 +00:00
parent a8452bf478
commit 69e096c120
1 changed files with 1 additions and 1 deletions
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2
sys/mips/include/cpuregs.h
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@ -524,7 +524,7 @@
#define MIPS_CONFIG0_MT_MASK 0x00000380 /* bits 9..7 MMU Type */
#define MIPS_CONFIG0_MT_SHIFT 7
#define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */
#define MIPS_CONFIG0_VI 0x00000004 /* instruction cache is virtual */
#define MIPS_CONFIG0_VI 0x00000008 /* instruction cache is virtual */
#define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */
#define MIPS_CONFIG1_TLBSZ_SHIFT 25