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mvebu_gpio: fix interrupt cause register configuration

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According to Armada 8k documentation, the interrupt cause register
(at offset 0x14) is RW0C. Update the configuration in attach and
the mvebu_gpio_isrc_eoi() to follow the description.

Reviewed by: mmel
Obtained from: Semihalf
Sponsored by: Marvell
Differential Revision: https://reviews.freebsd.org/D29013
This commit is contained in:
Marcin Wojtas 2021-02-24 18:02:40 +01:00
parent 0cc746f193
commit 819760b35f
1 changed files with 2 additions and 2 deletions
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4
sys/arm/mv/mvebu_gpio.c
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@ -333,7 +333,7 @@ mvebu_gpio_isrc_eoi(struct mvebu_gpio_softc *sc,
{ {
if (!mgi->is_level) if (!mgi->is_level)
intr_modify(sc, GPIO_INT_CAUSE, mgi, 1, 1); intr_modify(sc, GPIO_INT_CAUSE, mgi, 0, 1);
} }
static int static int
@ -778,7 +778,7 @@ mvebu_gpio_attach(device_t dev)
/* Init HW */ /* Init HW */
gpio_write(sc, GPIO_INT_MASK, pin, 0); gpio_write(sc, GPIO_INT_MASK, pin, 0);
gpio_write(sc, GPIO_INT_LEVEL_MASK, pin, 0); gpio_write(sc, GPIO_INT_LEVEL_MASK, pin, 0);
gpio_write(sc, GPIO_INT_CAUSE, pin, 1); gpio_write(sc, GPIO_INT_CAUSE, pin, 0);
gpio_write(sc, GPIO_DATA_IN_POL, pin, 1); gpio_write(sc, GPIO_DATA_IN_POL, pin, 1);
gpio_write(sc, GPIO_BLINK_ENA, pin, 0); gpio_write(sc, GPIO_BLINK_ENA, pin, 0);
} }