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Fix the offset for the CPU0 MPIC registers.

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Please note that only a subset of CPU0 registers are exported.  CPU1
registers are not touched.

Obtained from:	ARMADA38X Functional Specifications
Sponsored by:	Rubicon Communications, LLC (Netgate)
This commit is contained in:
loos 2017-05-17 22:05:07 +00:00
parent 1f5854075d
commit 921828e804
1 changed files with 1 additions and 1 deletions
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2
sys/boot/fdt/dts/arm/armada-38x.dtsi
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@ -419,7 +419,7 @@
mpic: interrupt-controller@20a00 { mpic: interrupt-controller@20a00 {
compatible = "marvell,mpic"; compatible = "marvell,mpic";
reg = <0x20a00 0x2d0>, <0x21070 0x58>; reg = <0x20a00 0x2d0>, <0x21870 0x58>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
interrupt-controller; interrupt-controller;