- Clean up Aperture Access Global Enable (APEN) bit access.
- Rename confusing AGP_INTEL_I845_MCHCFG to AGP_INTEL_I845_AGPM. - Move E7205 and E7505 from i8x5 to i8x0 family. It probably worked because the actual offset is the same. In fact, all three families have the bit at the exact same place. Only differences are name and width of the registers, i.e., NBXCFG (0x50, dword), RDCR (0x51, byte), AGPM (0x51, byte), MCHCFG (0x50, word) depending on the family of the chipsets.
This commit is contained in:
jkim
parent
602b5d480d
commit
a5dc00daab
@ -157,15 +157,8 @@ agp_intel_commit_gatt(device_t dev)
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pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4);
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}
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/* Enable things, clear errors etc. */
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/* Enable aperture accesses. */
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switch (type) {
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case 0x1a218086: /* i840 */
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case 0x25308086: /* i850 */
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case 0x25318086: /* i860 */
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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| (1 << 9)), 2);
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break;
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case 0x25008086: /* i820 */
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case 0x25018086: /* i820 */
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pci_write_config(dev, AGP_INTEL_I820_RDCR,
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@ -173,23 +166,31 @@ agp_intel_commit_gatt(device_t dev)
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| (1 << 1)), 1);
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break;
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case 0x1a308086: /* i845 */
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case 0x25608086: /* i845G */
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case 0x33408086: /* i855 */
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case 0x35808086: /* i855GM */
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case 0x255d8086: /* E7205 */
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case 0x25508086: /* E7505 */
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case 0x25708086: /* i865 */
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case 0x25788086: /* i875P */
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case 0x25608086: /* i845G */
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pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
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pci_write_config(dev, AGP_INTEL_I845_AGPM,
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(pci_read_config(dev, AGP_INTEL_I845_AGPM, 1)
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| (1 << 1)), 1);
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break;
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case 0x1a218086: /* i840 */
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case 0x25308086: /* i850 */
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case 0x25318086: /* i860 */
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case 0x255d8086: /* E7205 */
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case 0x25508086: /* E7505 */
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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| (1 << 9)), 2);
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break;
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default: /* Intel Generic (maybe) */
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pci_write_config(dev, AGP_INTEL_NBXCFG,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 10)) | (1 << 9), 4);
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}
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/* Clear errors. */
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switch (type) {
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case 0x1a218086: /* i840 */
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pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
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@ -197,14 +198,14 @@ agp_intel_commit_gatt(device_t dev)
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case 0x25008086: /* i820 */
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case 0x25018086: /* i820 */
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case 0x1a308086: /* i845 */
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case 0x25608086: /* i845G */
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case 0x25308086: /* i850 */
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case 0x33408086: /* i855 */
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case 0x255d8086: /* E7205 */
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case 0x25508086: /* E7505 */
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case 0x25318086: /* i860 */
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case 0x25708086: /* i865 */
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case 0x25788086: /* i875P */
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case 0x25608086: /* i845G */
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case 0x255d8086: /* E7205 */
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case 0x25508086: /* E7505 */
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pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
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break;
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default: /* Intel Generic (maybe) */
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@ -259,6 +260,7 @@ static int
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agp_intel_detach(device_t dev)
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{
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struct agp_intel_softc *sc;
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u_int32_t reg;
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int error;
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sc = device_get_softc(dev);
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@ -267,48 +269,37 @@ agp_intel_detach(device_t dev)
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if (error)
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return (error);
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/* Disable aperture accesses. */
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switch (pci_get_devid(dev)) {
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case 0x1a218086: /* i840 */
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case 0x25308086: /* i850 */
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case 0x25318086: /* i860 */
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printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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& ~(1 << 9)));
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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& ~(1 << 9)), 2);
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/* FALLTHRU */
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case 0x25008086: /* i820 */
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case 0x25018086: /* i820 */
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printf("%s: set RDCR to %x\n", __func__, (unsigned)
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(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
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& ~(1 << 1)));
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pci_write_config(dev, AGP_INTEL_I820_RDCR,
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(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
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& ~(1 << 1)), 1);
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/* FALLTHRU */
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reg = pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) & ~(1 << 1);
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printf("%s: set RDCR to %02x\n", __func__, reg & 0xff);
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pci_write_config(dev, AGP_INTEL_I820_RDCR, reg, 1);
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break;
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case 0x1a308086: /* i845 */
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case 0x25608086: /* i845G */
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case 0x33408086: /* i855 */
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case 0x35808086: /* i855GM */
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case 0x255d8086: /* E7205 */
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case 0x25508086: /* E7505 */
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case 0x25708086: /* i865 */
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case 0x25788086: /* i875P */
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printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
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(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
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& ~(1 << 1)));
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
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& ~(1 << 1)), 1);
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/* FALLTHRU */
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reg = pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) & ~(1 << 1);
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printf("%s: set AGPM to %02x\n", __func__, reg & 0xff);
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pci_write_config(dev, AGP_INTEL_I845_AGPM, reg, 1);
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break;
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case 0x1a218086: /* i840 */
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case 0x25308086: /* i850 */
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case 0x25318086: /* i860 */
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case 0x255d8086: /* E7205 */
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case 0x25508086: /* E7505 */
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reg = pci_read_config(dev, AGP_INTEL_MCHCFG, 2) & ~(1 << 9);
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printf("%s: set MCHCFG to %x04\n", __func__, reg & 0xffff);
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pci_write_config(dev, AGP_INTEL_MCHCFG, reg, 2);
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break;
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default: /* Intel Generic (maybe) */
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printf("%s: set NBXCFG to %x\n", __func__,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 9)));
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pci_write_config(dev, AGP_INTEL_NBXCFG,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 9)), 4);
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reg = pci_read_config(dev, AGP_INTEL_NBXCFG, 4) & ~(1 << 9);
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printf("%s: set NBXCFG to %08x\n", __func__, reg);
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pci_write_config(dev, AGP_INTEL_NBXCFG, reg, 4);
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}
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pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
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AGP_SET_APERTURE(dev, sc->initial_aperture);
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@ -73,11 +73,11 @@
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#define AGP_INTEL_ATTBASE 0xb8
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/*
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* Config offsets for Intel i820/i840/i845/i850/i860/i865 AGP chipsets.
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* Config offsets for Intel i8xx/E7xxx AGP chipsets.
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*/
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#define AGP_INTEL_MCHCFG 0x50
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#define AGP_INTEL_I820_RDCR 0x51
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#define AGP_INTEL_I845_MCHCFG 0x51
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#define AGP_INTEL_I845_AGPM 0x51
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#define AGP_INTEL_I8XX_ERRSTS 0xc8
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/*
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@ -157,15 +157,8 @@ agp_intel_commit_gatt(device_t dev)
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pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4);
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}
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/* Enable things, clear errors etc. */
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/* Enable aperture accesses. */
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switch (type) {
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case 0x1a218086: /* i840 */
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case 0x25308086: /* i850 */
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case 0x25318086: /* i860 */
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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| (1 << 9)), 2);
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break;
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case 0x25008086: /* i820 */
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case 0x25018086: /* i820 */
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pci_write_config(dev, AGP_INTEL_I820_RDCR,
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@ -173,23 +166,31 @@ agp_intel_commit_gatt(device_t dev)
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| (1 << 1)), 1);
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break;
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case 0x1a308086: /* i845 */
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case 0x25608086: /* i845G */
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case 0x33408086: /* i855 */
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case 0x35808086: /* i855GM */
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case 0x255d8086: /* E7205 */
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case 0x25508086: /* E7505 */
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case 0x25708086: /* i865 */
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case 0x25788086: /* i875P */
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case 0x25608086: /* i845G */
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pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
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pci_write_config(dev, AGP_INTEL_I845_AGPM,
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(pci_read_config(dev, AGP_INTEL_I845_AGPM, 1)
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| (1 << 1)), 1);
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break;
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case 0x1a218086: /* i840 */
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case 0x25308086: /* i850 */
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case 0x25318086: /* i860 */
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case 0x255d8086: /* E7205 */
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case 0x25508086: /* E7505 */
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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| (1 << 9)), 2);
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break;
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default: /* Intel Generic (maybe) */
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pci_write_config(dev, AGP_INTEL_NBXCFG,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 10)) | (1 << 9), 4);
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}
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/* Clear errors. */
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switch (type) {
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case 0x1a218086: /* i840 */
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pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
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@ -197,14 +198,14 @@ agp_intel_commit_gatt(device_t dev)
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case 0x25008086: /* i820 */
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case 0x25018086: /* i820 */
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case 0x1a308086: /* i845 */
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case 0x25608086: /* i845G */
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case 0x25308086: /* i850 */
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case 0x33408086: /* i855 */
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case 0x255d8086: /* E7205 */
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case 0x25508086: /* E7505 */
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case 0x25318086: /* i860 */
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case 0x25708086: /* i865 */
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case 0x25788086: /* i875P */
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case 0x25608086: /* i845G */
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case 0x255d8086: /* E7205 */
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case 0x25508086: /* E7505 */
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pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
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break;
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default: /* Intel Generic (maybe) */
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@ -259,6 +260,7 @@ static int
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agp_intel_detach(device_t dev)
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{
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struct agp_intel_softc *sc;
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u_int32_t reg;
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int error;
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sc = device_get_softc(dev);
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@ -267,48 +269,37 @@ agp_intel_detach(device_t dev)
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if (error)
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return (error);
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/* Disable aperture accesses. */
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switch (pci_get_devid(dev)) {
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case 0x1a218086: /* i840 */
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case 0x25308086: /* i850 */
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case 0x25318086: /* i860 */
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printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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& ~(1 << 9)));
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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& ~(1 << 9)), 2);
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/* FALLTHRU */
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case 0x25008086: /* i820 */
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case 0x25018086: /* i820 */
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printf("%s: set RDCR to %x\n", __func__, (unsigned)
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(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
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& ~(1 << 1)));
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pci_write_config(dev, AGP_INTEL_I820_RDCR,
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(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
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& ~(1 << 1)), 1);
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/* FALLTHRU */
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reg = pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) & ~(1 << 1);
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printf("%s: set RDCR to %02x\n", __func__, reg & 0xff);
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pci_write_config(dev, AGP_INTEL_I820_RDCR, reg, 1);
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break;
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case 0x1a308086: /* i845 */
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case 0x25608086: /* i845G */
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case 0x33408086: /* i855 */
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case 0x35808086: /* i855GM */
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case 0x255d8086: /* E7205 */
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case 0x25508086: /* E7505 */
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case 0x25708086: /* i865 */
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case 0x25788086: /* i875P */
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printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
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(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
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& ~(1 << 1)));
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
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& ~(1 << 1)), 1);
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/* FALLTHRU */
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reg = pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) & ~(1 << 1);
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printf("%s: set AGPM to %02x\n", __func__, reg & 0xff);
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pci_write_config(dev, AGP_INTEL_I845_AGPM, reg, 1);
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break;
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case 0x1a218086: /* i840 */
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case 0x25308086: /* i850 */
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case 0x25318086: /* i860 */
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case 0x255d8086: /* E7205 */
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case 0x25508086: /* E7505 */
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reg = pci_read_config(dev, AGP_INTEL_MCHCFG, 2) & ~(1 << 9);
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printf("%s: set MCHCFG to %x04\n", __func__, reg & 0xffff);
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pci_write_config(dev, AGP_INTEL_MCHCFG, reg, 2);
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break;
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default: /* Intel Generic (maybe) */
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printf("%s: set NBXCFG to %x\n", __func__,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 9)));
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pci_write_config(dev, AGP_INTEL_NBXCFG,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 9)), 4);
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reg = pci_read_config(dev, AGP_INTEL_NBXCFG, 4) & ~(1 << 9);
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printf("%s: set NBXCFG to %08x\n", __func__, reg);
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pci_write_config(dev, AGP_INTEL_NBXCFG, reg, 4);
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}
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pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
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AGP_SET_APERTURE(dev, sc->initial_aperture);
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@ -73,11 +73,11 @@
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#define AGP_INTEL_ATTBASE 0xb8
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/*
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* Config offsets for Intel i820/i840/i845/i850/i860/i865 AGP chipsets.
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* Config offsets for Intel i8xx/E7xxx AGP chipsets.
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*/
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#define AGP_INTEL_MCHCFG 0x50
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#define AGP_INTEL_I820_RDCR 0x51
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#define AGP_INTEL_I845_MCHCFG 0x51
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#define AGP_INTEL_I845_AGPM 0x51
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#define AGP_INTEL_I8XX_ERRSTS 0xc8
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/*
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Block a user