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Get rid of redundant setting of interrupt enable bit when restoring the status

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register from the PCB.

Remove a couple of misleading comments while I am here. The comments are
misleading because they imply that interrupts will be enabled after the
status register is restored from the PCB. This is not the case because
the processor is at the exception level (SR_EXL is set).

Approved by: imp (mentor)
This commit is contained in:
Neel Natu 2010-01-21 02:21:31 +00:00
parent 9e3ed0a7fe
commit b2edbc662e
1 changed files with 1 additions and 13 deletions
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14
sys/mips/mips/exception.S
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@ -581,16 +581,10 @@ NNON_LEAF(MipsUserGenException, STAND_FRAME_SIZE, ra)
#ifdef TARGET_OCTEON
and k0, k0, ~(MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX)
#endif
or k0, k0, (MIPS_SR_INT_IE)
.set noat
RESTORE_U_PCB_REG(AT, AST, k1)
/*
* The restoration of the user SR must be done only after
* k1 is no longer needed. Otherwise, k1 will get clobbered after
* interrupts are enabled.
*/
mtc0 k0, COP_0_STATUS_REG # still exeption level
mtc0 k0, COP_0_STATUS_REG # still exception level
ITLBNOPFIX
sync
eret
@ -814,15 +808,9 @@ NNON_LEAF(MipsUserIntr, STAND_FRAME_SIZE, ra)
#ifdef TARGET_OCTEON
and k0, k0, ~(MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX)
#endif
or k0, k0, (MIPS_SR_INT_IE|SR_EXL)
.set noat
RESTORE_U_PCB_REG(AT, AST, k1)
/*
* The restoration of the user SR must be done only after
* k1 is no longer needed. Otherwise, k1 will get clobbered after
* interrupts are enabled.
*/
mtc0 k0, COP_0_STATUS_REG # SR with EXL set.
ITLBNOPFIX
sync