d/freebsd-skq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Defer allowing async. requests after self ID's have received.

Browse Source 
This should fix some problem of SBP2 device probing.

Prior to rev 1.41, we keep writing the register while bus reset phase.
But in rev 1.41, we ignore successive bus reset events and some chips seem to
clear the register after we write to it.

Tested by: Michael Reifenberger <root@nihil.reifenberger.com>
This commit is contained in:
simokawa 2003-03-03 04:10:56 +00:00
parent 23b4d02e59
commit ba9b8f5cfc
1 changed files with 6 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
sys/dev/firewire/fwohci.c
View File

@ -1783,13 +1783,6 @@ fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count)
OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
#endif
fw_busreset(fc);
OWRITE(sc, OHCI_AREQHI, 1 << 31);
/* XXX insecure ?? */
OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
OWRITE(sc, OHCI_PREQLO, 0xffffffff);
OWRITE(sc, OHCI_PREQUPPER, 0x10000);
}
busresetout:
if((stat & OHCI_INT_DMA_IR )){
@ -1857,6 +1850,12 @@ busresetout:
#endif
/* Enable bus reset interrupt */
OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
/* Allow async. request to us */
OWRITE(sc, OHCI_AREQHI, 1 << 31);
/* XXX insecure ?? */
OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
OWRITE(sc, OHCI_PREQLO, 0xffffffff);
OWRITE(sc, OHCI_PREQUPPER, 0x10000);
/*
** Checking whether the node is root or not. If root, turn on
** cycle master.