Add bus space barriers for page switches missed in r260050.
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@ -420,7 +420,11 @@ ed_stop_hw(struct ed_softc *sc)
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/*
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* Stop everything on the interface, and select page 0 registers.
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*/
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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/*
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* Wait for interface to enter stopped state, but limit # of checks to
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@ -528,7 +532,11 @@ ed_init_locked(struct ed_softc *sc)
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/*
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* Set interface for page 0, Remote DMA complete, Stopped
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*/
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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if (sc->isa16bit)
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/*
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@ -649,7 +657,11 @@ ed_xmit(struct ed_softc *sc)
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/*
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* Set NIC for page 0 register access
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*/
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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/*
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* Set TX buffer start page
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@ -666,7 +678,11 @@ ed_xmit(struct ed_softc *sc)
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/*
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* Set page 0, Remote DMA complete, Transmit Packet, and *Start*
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*/
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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sc->xmit_busy = 1;
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/*
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@ -913,7 +929,11 @@ ed_rint(struct ed_softc *sc)
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/*
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* Set NIC to page 0 registers to update boundry register
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*/
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_BNRY, boundry);
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/*
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@ -947,7 +967,11 @@ edintr(void *arg)
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/*
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* Set NIC to page 0 registers
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*/
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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/*
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* loop until there are no more new interrupts. When the card goes
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@ -1165,7 +1189,11 @@ edintr(void *arg)
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* set in the transmit routine, is *okay* - it is 'edge'
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* triggered from low to high)
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*/
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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/*
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* If the Network Talley Counters overflow, read them to reset
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@ -1367,7 +1395,11 @@ ed_pio_readmem(struct ed_softc *sc, bus_size_t src, uint8_t *dst,
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{
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/* Regular Novell cards */
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/* select page 0 registers */
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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/* round up to a word */
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if (amount & 1)
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@ -1400,7 +1432,11 @@ ed_pio_writemem(struct ed_softc *sc, uint8_t *src, uint16_t dst, uint16_t len)
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int maxwait = 200; /* about 240us */
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/* select page 0 registers */
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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/* reset remote DMA complete flag */
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ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
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@ -1457,7 +1493,11 @@ ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, bus_size_t dst)
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dma_len++;
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/* select page 0 registers */
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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/* reset remote DMA complete flag */
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ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
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@ -1587,7 +1627,11 @@ ed_setrcr(struct ed_softc *sc)
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* runts and packets with CRC & alignment errors.
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*/
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/* Set page 0 registers */
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
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ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
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@ -1609,7 +1653,11 @@ ed_setrcr(struct ed_softc *sc)
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ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
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/* Set page 0 registers */
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
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} else {
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@ -1622,6 +1670,8 @@ ed_setrcr(struct ed_softc *sc)
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ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
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/* Set page 0 registers */
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
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ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
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@ -565,7 +565,11 @@ ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, bus_size_t dst)
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int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
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/* select page 0 registers */
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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/* reset remote DMA complete flag */
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ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
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