Change ordering of SPDIF register pokes. SPDIF enable needs to be the
last poke in sequence. Enabling SPDIF was coercing output rate to 48K, not good for 44.1K tracks.
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cbf67f9c44
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@ -307,8 +307,6 @@ static void
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cmi_spdif_speed(struct cmi_info *cmi, int speed) {
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u_int32_t fcr1, lcr, mcr;
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mcr = 0;
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if (speed >= 44100) {
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fcr1 = CMPCI_REG_SPDIF0_ENABLE;
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lcr = CMPCI_REG_XSPDIF_ENABLE;
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@ -318,12 +316,12 @@ cmi_spdif_speed(struct cmi_info *cmi, int speed) {
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fcr1 = mcr = lcr = 0;
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}
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cmi_partial_wr4(cmi, CMPCI_REG_FUNC_1, 0,
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CMPCI_REG_SPDIF0_ENABLE, fcr1);
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cmi_partial_wr4(cmi, CMPCI_REG_MISC, 0,
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CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr);
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cmi_partial_wr4(cmi, CMPCI_REG_LEGACY_CTRL, 0,
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CMPCI_REG_XSPDIF_ENABLE, lcr);
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cmi_partial_wr4(cmi, CMPCI_REG_FUNC_1, 0,
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CMPCI_REG_SPDIF0_ENABLE, fcr1);
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}
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/* ------------------------------------------------------------------------- */
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