Change ordering of SPDIF register pokes. SPDIF enable needs to be the

last poke in sequence.  Enabling SPDIF was coercing output rate to
48K, not good for 44.1K tracks.
This commit is contained in:
orion 2001-03-21 12:51:37 +00:00
parent cbf67f9c44
commit ebb670b334

View File

@ -307,8 +307,6 @@ static void
cmi_spdif_speed(struct cmi_info *cmi, int speed) {
u_int32_t fcr1, lcr, mcr;
mcr = 0;
if (speed >= 44100) {
fcr1 = CMPCI_REG_SPDIF0_ENABLE;
lcr = CMPCI_REG_XSPDIF_ENABLE;
@ -318,12 +316,12 @@ cmi_spdif_speed(struct cmi_info *cmi, int speed) {
fcr1 = mcr = lcr = 0;
}
cmi_partial_wr4(cmi, CMPCI_REG_FUNC_1, 0,
CMPCI_REG_SPDIF0_ENABLE, fcr1);
cmi_partial_wr4(cmi, CMPCI_REG_MISC, 0,
CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr);
cmi_partial_wr4(cmi, CMPCI_REG_LEGACY_CTRL, 0,
CMPCI_REG_XSPDIF_ENABLE, lcr);
cmi_partial_wr4(cmi, CMPCI_REG_FUNC_1, 0,
CMPCI_REG_SPDIF0_ENABLE, fcr1);
}
/* ------------------------------------------------------------------------- */