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add QCA955x PCIe configuration registers.

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These are /not/ absolute addresses, as the QCA955x SoC has 2 PCIe RC's
(and 1 PCIe EP.)
This commit is contained in:
adrian 2015-03-21 06:00:46 +00:00
parent 9ce94e7c25
commit f5a9460e2b
1 changed files with 10 additions and 0 deletions
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10
sys/mips/atheros/qca955xreg.h
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@ -205,4 +205,14 @@
#define QCA955X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8)
#define QCA955X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac)
/* PCIe control block - relative to PCI_CTRL_BASE0/PCI_CTRL_BASE1 */
#define QCA955X_PCI_APP 0x0
#define QCA955X_PCI_APP_LTSSM_ENABLE (1 << 0)
#define QCA955X_PCI_RESET 0x18
#define QCA955X_PCI_RESET_LINK_UP (1 << 0)
#define QCA955X_PCI_INTR_STATUS 0x4c
#define QCA955X_PCI_INTR_MASK 0x50
#define QCA955X_PCI_INTR_DEV0 (1 << 14)
#endif /* __QCA955XREG_H__ */