Automatically enable CPU_ENABLE_SSE (detect and enable SSE instructions)

if compiling with I686_CPU as a target.  CPU_DISABLE_SSE will prevent
this from happening and will guarantee the code is not compiled in.

I am still not happy with this, but gcc is now generating code that uses
these instructions if you set CPUTYPE to p3/p4 or athlon-4/mp/xp or higher.

sys/amd64/amd64/fpu.c

@@ -88,6 +88,13 @@
 #include <isa/isavar.h>
 #endif
 
+#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU)
+#define CPU_ENABLE_SSE
+#endif
+#if defined(CPU_DISABLE_SSE)
+#undef CPU_ENABLE_SSE
+#endif
+
 /*
  * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
  */

sys/amd64/amd64/initcpu.c

@@ -40,6 +40,13 @@
 #include <machine/md_var.h>
 #include <machine/specialreg.h>
 
+#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU)
+#define CPU_ENABLE_SSE
+#endif
+#if defined(CPU_DISABLE_SSE)
+#undef CPU_ENABLE_SSE
+#endif
+
 void initializecpu(void);
 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
 void	enable_K5_wt_alloc(void);

sys/amd64/amd64/machdep.c

@@ -130,6 +130,13 @@ extern void initializecpu(void);
 #define	CS_SECURE(cs)		(ISPL(cs) == SEL_UPL)
 #define	EFL_SECURE(ef, oef)	((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
 
+#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU)
+#define CPU_ENABLE_SSE
+#endif
+#if defined(CPU_DISABLE_SSE)
+#undef CPU_ENABLE_SSE
+#endif
+
 static void cpu_startup(void *);
 #ifdef CPU_ENABLE_SSE
 static void set_fpregs_xmm(struct save87 *, struct savexmm *);

sys/amd64/isa/npx.c

@@ -88,6 +88,13 @@
 #include <isa/isavar.h>
 #endif
 
+#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU)
+#define CPU_ENABLE_SSE
+#endif
+#if defined(CPU_DISABLE_SSE)
+#undef CPU_ENABLE_SSE
+#endif
+
 /*
  * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
  */

sys/conf/options.i386

@@ -64,6 +64,7 @@ CYRIX_CACHE_REALLY_WORKS	opt_cpu.h
 NO_MEMORY_HOLE			opt_cpu.h
 CPU_ENABLE_SSE			opt_cpu.h
 CPU_ATHLON_SSE_HACK		opt_cpu.h
+CPU_DISABLE_SSE			opt_cpu.h
 
 # The CPU type affects the endian conversion functions all over the kernel.
 I386_CPU		opt_global.h

sys/conf/options.pc98

@@ -62,6 +62,7 @@ CYRIX_CACHE_REALLY_WORKS	opt_cpu.h
 NO_MEMORY_HOLE			opt_cpu.h
 CPU_ENABLE_SSE			opt_cpu.h
 CPU_ATHLON_SSE_HACK		opt_cpu.h
+CPU_DISABLE_SSE			opt_cpu.h
 
 # The CPU type affects the endian conversion functions all over the kernel.
 I386_CPU		opt_global.h

sys/i386/conf/NOTES

@@ -87,7 +87,9 @@ cpu		I686_CPU		# aka Pentium Pro(tm)
 #
 # CPU_ELAN enables support for AMDs ElanSC520 CPU.
 #
-# CPU_ENABLE_SSE enables SSE/MMX2 instructions support.
+# CPU_ENABLE_SSE enables SSE/MMX2 instructions support.  This is default
+# on I686_CPU and above.
+# CPU_DISABLE_SSE explicitly prevent I686_CPU from turning on SSE.
 #
 # CPU_FASTER_5X86_FPU enables faster FPU exception handler.
 #
@@ -155,6 +157,7 @@ options 	CPU_DIRECT_MAPPED_CACHE
 options 	CPU_DISABLE_5X86_LSSER
 options		CPU_ELAN
 options 	CPU_ENABLE_SSE
+#options 	CPU_DISABLE_SSE
 options 	CPU_FASTER_5X86_FPU
 options 	CPU_I486_ON_386
 options 	CPU_IORT

sys/i386/i386/initcpu.c

@@ -40,6 +40,13 @@
 #include <machine/md_var.h>
 #include <machine/specialreg.h>
 
+#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU)
+#define CPU_ENABLE_SSE
+#endif
+#if defined(CPU_DISABLE_SSE)
+#undef CPU_ENABLE_SSE
+#endif
+
 void initializecpu(void);
 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
 void	enable_K5_wt_alloc(void);

sys/i386/i386/machdep.c

@@ -130,6 +130,13 @@ extern void initializecpu(void);
 #define	CS_SECURE(cs)		(ISPL(cs) == SEL_UPL)
 #define	EFL_SECURE(ef, oef)	((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
 
+#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU)
+#define CPU_ENABLE_SSE
+#endif
+#if defined(CPU_DISABLE_SSE)
+#undef CPU_ENABLE_SSE
+#endif
+
 static void cpu_startup(void *);
 #ifdef CPU_ENABLE_SSE
 static void set_fpregs_xmm(struct save87 *, struct savexmm *);

sys/i386/isa/npx.c

@@ -88,6 +88,13 @@
 #include <isa/isavar.h>
 #endif
 
+#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU)
+#define CPU_ENABLE_SSE
+#endif
+#if defined(CPU_DISABLE_SSE)
+#undef CPU_ENABLE_SSE
+#endif
+
 /*
  * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
  */

sys/i386/linux/linux_ptrace.c

@@ -28,6 +28,8 @@
  * $FreeBSD$
  */
 
+#include "opt_cpu.h"
+
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/lock.h>
@@ -46,6 +48,13 @@
 #include <i386/linux/linux_proto.h>
 #include <compat/linux/linux_util.h>
 
+#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU)
+#define CPU_ENABLE_SSE
+#endif
+#if defined(CPU_DISABLE_SSE)
+#undef CPU_ENABLE_SSE
+#endif
+
 /*
  *   Linux ptrace requests numbers. Mostly identical to FreeBSD,
  *   except for MD ones and PT_ATTACH/PT_DETACH.
@@ -334,7 +343,7 @@ linux_ptrace(struct thread *td, struct linux_ptrace_args *uap)
 		}
 		break;
 	case PTRACE_SETFPXREGS:
-#ifdef CPU_ENABLE_SSA
+#ifdef CPU_ENABLE_SSE
 		error = copyin((caddr_t)uap->data, &r.fpxreg,
 		    sizeof(r.fpxreg));
 		if (error)

sys/pc98/i386/machdep.c

@@ -135,6 +135,13 @@ extern void initializecpu(void);
 #define	CS_SECURE(cs)		(ISPL(cs) == SEL_UPL)
 #define	EFL_SECURE(ef, oef)	((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
 
+#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU)
+#define CPU_ENABLE_SSE
+#endif
+#if defined(CPU_DISABLE_SSE)
+#undef CPU_ENABLE_SSE
+#endif
+
 static void cpu_startup(void *);
 #ifdef CPU_ENABLE_SSE
 static void set_fpregs_xmm(struct save87 *, struct savexmm *);

sys/pc98/pc98/machdep.c

@@ -135,6 +135,13 @@ extern void initializecpu(void);
 #define	CS_SECURE(cs)		(ISPL(cs) == SEL_UPL)
 #define	EFL_SECURE(ef, oef)	((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
 
+#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU)
+#define CPU_ENABLE_SSE
+#endif
+#if defined(CPU_DISABLE_SSE)
+#undef CPU_ENABLE_SSE
+#endif
+
 static void cpu_startup(void *);
 #ifdef CPU_ENABLE_SSE
 static void set_fpregs_xmm(struct save87 *, struct savexmm *);