5416 and similar chips grew another region in the pci clock domain
where register accesses do not pass through the byte-lane hardware; extend the register op macros to deal with this MFC after: 1 week
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@ -87,8 +87,11 @@ extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
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#define AH_BIG_ENDIAN 4321
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#if _BYTE_ORDER == _BIG_ENDIAN
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#define OS_REG_UNSWAPPED(_reg) \
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(((_reg) >= 0x4000 && (_reg) < 0x5000) || \
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((_reg) >= 0x7000 && (_reg) < 0x8000))
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#define OS_REG_WRITE(_ah, _reg, _val) do { \
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if ( (_reg) >= 0x4000 && (_reg) < 0x5000) \
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if (OS_REG_UNSWAPPED(_reg)) \
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bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \
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(bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \
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else \
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@ -96,12 +99,13 @@ extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
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(bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \
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} while (0)
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#define OS_REG_READ(_ah, _reg) \
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(((_reg) >= 0x4000 && (_reg) < 0x5000) ? \
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(OS_REG_UNSWAPPED(_reg) ? \
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bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \
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(bus_space_handle_t)(_ah)->ah_sh, (_reg)) : \
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bus_space_read_stream_4((bus_space_tag_t)(_ah)->ah_st, \
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(bus_space_handle_t)(_ah)->ah_sh, (_reg)))
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#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
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#define OS_REG_UNSWAPPED(_reg) (0)
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#define OS_REG_WRITE(_ah, _reg, _val) \
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bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \
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(bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val))
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