Commit Graph

130 Commits

Author SHA1 Message Date
imp
05ddd02b52 No need to have an extra layer of indirection here. Call the sdhci_cam_requiest
routine directly when handling a MMIO request.
2020-01-27 22:20:02 +00:00
imp
bce1c3d873 Create a convenince wrapper to fill in a CAM_PATH_INQ request for MMC sims. Pass
in the parameters needed for the different sims, but it's almost all identical.
2020-01-27 22:19:55 +00:00
imp
a476ba06d5 Regularize my copyright notice
o Remove All Rights Reserved from my notices
o imp@FreeBSD.org everywhere
o regularize punctiation, eliminate date ranges
o Make sure that it's clear that I don't claim All Rights reserved by listing
  All Rights Reserved on same line as other copyright holders (but not
  me). Other such holders are also listed last where it's clear.
2019-12-04 16:56:11 +00:00
ian
8eb4642025 Relax the sdhci(4) check that filters out the 1.8v voltage option unless
the slot is flagged as 'embedded'.

The features related to embedded and shared slots were added in v3.0 of
the sdhci spec.  Hardware prior to v3 sometimes supported 1.8v on non-
removable devices in embedded systems, but had no way to indicate that
via the standard sdhci registers (instead they use out of band metadata
such as FDT data).

This change adds the controller specification version to the check for
whether to filter out the 1.8v selection.  On older hardware, the 1.8v
option is allowed to remain.  On 3.0 or later it still requires the
embedded-slot flag to remain.

This is part of the fix for PR 241301 (eMMC not detected on Beaglebone).
Changes to the sdhci_ti driver are also needed for a full fix.

PR:		241301
2019-10-16 16:03:19 +00:00
ian
0b3966a2fa Allow the sdhci timeout sysctl var to be set as a tunable. Also, add a
missing newline in a warning printf.
2019-08-10 20:03:14 +00:00
ganbold
4684fc8cb7 Add emmc support for Rockchip RK3399 SoC.
Tested on NanoPC-T4 board.

Reviewed by:	manu
Differential Revision:	https://reviews.freebsd.org/D20156
2019-07-20 02:53:06 +00:00
loos
c43b38ad99 Add support for the GPIO SD Card VCC regulator/switch and the GPIO SD Card
detection pins to the Marvell Xenon SDHCI controller.

These features are enable by 'vqmmc-supply' and 'cd-gpios' properties in the
DTS.

This fixes the SD Card detection on espressobin.

Sponsored by:	Rubicon Communications, LLC (Netgate)
2019-06-10 21:50:07 +00:00
bz
dc3514f82c Improve sdhci slot_printf() debug printing.
Currently slot_printf() uses two printf() calls to print the
device-slot name, and actual message. When other printf()s are
ongoing in parallel this can lead to interleaved message on the console,
which is especially unhelpful for debugging or error messages.

Take a hit on the stack and vsnprintf() the message to the buffer.
This way it can be printed along with the device-slot name in one go
avoiding console gibberish.

Reviewed by:	marius
MFC after:	2 weeks
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D19747
2019-06-08 15:24:03 +00:00
bz
e50eccff2b Introduce sim_dev and cam_sim_alloc_dev().
Add cam_sim_alloc_dev() as a wrapper to cam_sim_alloc() which takes
a device_t instead of the unit_number (which we can derive from the
dev again).

Add device_t sim_dev to struct cam_sim. It will be used to pass through
the bus for cases when both sides of CAM speak newbus already and we want
to link them (yet make the calls through CAM for now).

SDIO will be the first consumer of this. For that make use of
cam_sim_alloc_dev() in sdhci under MMCCAM.

This will also allow people to start iterating more on the idea
to newbus-ify CAM without changing 50+ device drivers from the start.
Also to be clear there are callers to cam_sim_alloc() which do not
have a device_t (e.g., XPT) or provide their own unit number so we cannot
simply switch the KPI entirely.

Submitted by:	kibab (original idea, see https://reviews.freebsd.org/D12467)
Reviewed by:	imp, chuck
MFC after:	2 weeks
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D19746
2019-06-08 15:19:50 +00:00
bz
85107dcffe Improve error/debug messages in sdhci.c
When starting a command also print the opcode and flags.
More consitently print flags as hex.
Use slot_printf rather than printf in one case.

MFC after:		6 weeks
Reviewed by:		marius, kibab, imp
Sponsored by:		The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D19748
2019-06-01 14:39:12 +00:00
kibab
49c5ad42bb Implement CMD53 block mode support for SDHCI and AllWinner-based boards
If a custom block size requested, use it, otherwise revert to the previous logic
of using just a data size if it's less than MMC_BLOCK_SIZE, and MMC_BLOCK_SIZE otherwise.

Reviewed by:	bz
Approved by:	imp (mentor)
Differential Revision:	https://reviews.freebsd.org/D19783
2019-04-10 19:53:36 +00:00
kibab
10ac8498c5 Use information about max data size that the controller is able to operate
Using DFLTPHYS/MAXPHYS is not always OK, instead make it possible for the
controller driver to provide maximum data size to MMCCAM, and use it there.

The old stack already does this.

Reviewed by:	manu
Approved by:	imp (mentor)
Differential Revision:	https://reviews.freebsd.org/D15892
2019-04-01 18:49:39 +00:00
bz
1ca6c95b99 Whitespace cleanup in sdhci.c
No functional changes.  Replace whitespace by tabs, indent with 4 spaces,
coalesce multi-line shorter than 80 characters,

MFC after:	2 weeks
Sponsored by:	The FreeBSD Foundation
2019-03-21 10:50:36 +00:00
bz
b5e8e61ac3 Align struct sdhci_slot MMCCAM members.
Whitespace only, no functional change.

MFC after:	2 weeks
Sponsored by:	The FreeBSD Foundation
2019-03-21 10:23:02 +00:00
marius
608c05f554 o Don't allocate resources for SDMA in sdhci(4) if the controller or the
front-end doesn't support SDMA or the latter implements a platform-
  specific transfer method instead. While at it, factor out allocation
  and freeing of SDMA resources to sdhci_dma_{alloc,free}() in order to
  keep the code more readable when adding support for ADMA variants.

o Base the size of the SDMA bounce buffer on MAXPHYS up to the maximum
  of 512 KiB instead of using a fixed 4-KiB-buffer. With the default
  MAXPHYS of 128 KiB and depending on the controller and medium, this
  reduces the number of SDHCI interrupts by a factor of ~16 to ~32 on
  sequential reads while an increase of throughput of up to ~84 % was
  seen.

  Front-ends for broken controllers that only support an SDMA buffer
  boundary of a specific size may set SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY
  and supply a size via struct sdhci_slot. According to Linux, only
  Qualcomm MSM-type SDHCI controllers are affected by this, though.

  Requested by: Shreyank Amartya (unconditional bump to 512 KiB)

o Introduce a SDHCI_DEPEND macro for specifying the dependency of the
  front-end modules on the sdhci(4) one and bump the module version
  of sdhci(4) to 2 via an also newly introduced SDHCI_VERSION in order
  to ensure that all components are in sync WRT struct sdhci_slot.

o In sdhci(4):
  - Make pointers const were applicable,
  - replace a few device_printf(9) calls with slot_printf() for
    consistency, and
  - sync some local functions with their prototypes WRT static.
2018-12-30 23:08:06 +00:00
manu
e22b714d0f sdhci_xenon: Add Marvell 8k compatible string
Sponsored by:	Rubicon Communications, LLC ("Netgate")
2018-12-12 22:09:35 +00:00
marius
45b15c02f0 For consistency within the front-end, prefer SDHCI_{READ,WRITE}_{2,4}()
to sdhci_acpi_{read,write}_{2,4}() in the sdhci_acpi_set_uhs_timing()
added in r340543.
2018-11-19 23:56:33 +00:00
marius
b25f54118a Add a quirk handling for AMDI0040 controllers allowing them to do HS400.
Submitted by:	Shreyank Amartya (original version)
2018-11-18 00:52:27 +00:00
takawata
5499ddf2ec Distinguish _CID match and _HID match and make lower priority probe
when _CID match.

Reviewed by: jhb, imp
Differential Revision:https://reviews.freebsd.org/D16468
2018-10-26 00:05:46 +00:00
gonzo
afca8086a5 [sdhci] Add ACPI identifier for AMD eMMC 5.0 controller
Submitted by:	Rajesh Kumar <rajfbsd@gmail.com>
Approved by:	re (rgrimes)
Differential Revision:	https://reviews.freebsd.org/D17189
2018-09-29 00:35:36 +00:00
marius
77f44c41c2 - Explicitly compare a pointer to NULL. The __builtin_expect() of clang
3.4.1 otherwise isn't able to cope with the expression.
- Fix a nearby whitespace bug.

Approved by:	re (gjb, kib)
2018-09-06 21:09:54 +00:00
manu
2a0d911790 arm64: GENERIC-MMCCAM: Fix build and module depend
Fix the build of the GENERIC-MMCCAM kernel config after the sdhci_xenon
driver was commited.
While here correct sdhci_fdt and tegra_sdhci, even with MMCCAM they do
need to depend on sdhci(4)

Reported by:	Reshetnikov Dmitriy <genserg@hotmail.com>
Approved by:	re (kib)
Sponsored by:	Rubicon Communications, LLC ("NetGate")
2018-08-29 14:01:27 +00:00
marius
0b4e2ed1d7 - According to section 2.2.5 of the SDHCI specification version 4.20,
SDHCI_TRNS_ACMD12 is to be set only for multiple-block read/write
  commands without data length information, so don't unconditionally
  set this bit. The result matches what e. g. Linux does.
- Section 2.2.19 of the SDHCI specification version 4.20 states that
  SDHCI_ACMD12_ERR should be only valid if SDHCI_INT_ACMD12ERR is set
  and hardware may clear SDHCI_ACMD12_ERR when SDHCI_INT_ACMD12ERR is
  cleared (differing silicon behavior is specifically allowed, though).
  Thus, read SDHCI_ACMD12_ERR before clearing SDHCI_INT_ACMD12ERR.
  While at it, use the 16-bit accessor rather than the 32-bit one for
  reading the 16-bit SDHCI_ACMD12_ERR.
- SDHCI_INT_TUNEERR isn't one of the ROC bits in SDHCI_INT_STATUS so
  clear it explicitly.
- Add missing prototypes and sort them.
2018-08-23 17:50:41 +00:00
loos
21f5deb5e6 Add support to the Marvell Xenon SDHCI controller.
Tested on Espresso.bin (37x0) and Macchiato.bin (8k) with SD cards and
eMMCs.

Obtained from:	pfSense
Sponsored by:	Rubicon Communications, LLC (Netgate)
2018-08-14 16:33:30 +00:00
marius
88409bdbbf The broken DDR52 support of Intel Bay Trail eMMC controllers rumored
in the commit log of r321385 has been confirmed via the public VLI54
erratum. Thus, stop advertising DDR52 for these controllers.
Note that this change should hardly make a difference in practice as
eMMC chips from the same era as these SoCs most likely support HS200
at least, probably even up to HS400ES.
2018-05-14 21:46:06 +00:00
manu
fb8d1c20e3 Fix build when option MMCCAM is defined. 2018-03-08 22:49:36 +00:00
ian
8e9acc464c Don't call sdhci_cleanup_slot() if sdhci_init_slot() never got called.
Also, do callout_init() very early in attach, so that callout_drain()
can be called in detach without worrying about whether it ever got init'd.
2018-02-17 23:39:10 +00:00
br
85a51c91ee Add support for SDHCI controller found in Qualcomm Snapdragon 410e.
Tested on DragonBoard 410c.

Sponsored by:	DARPA, AFRL
2018-01-25 17:00:35 +00:00
marius
3d1d28421e Fix a bug introduced in r327339; at the point in time re-tuning is
executed, the interrupt aggregation code might have disabled the
SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE bits in slot->intmask
and the SDHCI_SIGNAL_ENABLE register respectively. So when restoring
the interrupt masks based on the previous contents of slot->intmask
in sdhci_exec_tuning(), ensure that the SDHCI_INT_ENABLE register
doesn't lose these two bits.
While at it and in the spirit of r327339, let sdhci_tuning_intmask()
set the tuning error and re-tuning interrupt bits based on the
SDHCI_TUNING_ENABLED rather than the SDHCI_TUNING_SUPPORTED flag
being set, i. e. only when (re-)tuning is actually used. Currently,
this changes makes no net difference, though.
2018-01-13 16:21:13 +00:00
marius
cff3710332 - There is no need to keep the tuning error and re-tuning interrupts
enabled (though, no interrupt generation enabled for them) all the
  time as soon as (re-)tuning is supported; only enable them and let
  them generate interrupts when actually using (re-)tuning.
- Also disable all interrupts except SDHCI_INT_DATA_AVAIL ones while
  executing tuning and not just their signaling.
2017-12-29 12:48:19 +00:00
marius
b86a7c3d00 Probe Intel Denverton eMMC 5.0 controllers. 2017-12-28 22:03:08 +00:00
pfg
1537078d8f sys/dev: further adoption of SPDX licensing ID tags.
Mainly focus on files that use BSD 2-Clause license, however the tool I
was using misidentified many licenses so this was mostly a manual - error
prone - task.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.
2017-11-27 14:52:40 +00:00
ian
0a072e9bda Actually release resources in detach() rather than just returning EBUSY.
This will enable use of 'devctl disable', allow creation of a module, etc.
2017-10-27 17:21:43 +00:00
kibab
7e63745e11 Rename sdhci_cam_start_slot() into sdhci_start_slot()
This change allows to just call sdhci_start_slot() in SDHCI drivers
and not to think about which stack handles the operation.

As a side effect, this will also fix MMCCAM with sdhci_acpi driver.

Approved by:	imp (mentor)
Differential Revision:	https://reviews.freebsd.org/D12471
2017-09-24 09:05:35 +00:00
marius
ed7adc5aa8 - Check the slot type capability, set SDHCI_SLOT_{EMBEDDED,NON_REMOVABLE}
for embedded slots. Fail in the sdhci(4) initialization for slot type
  shared, which is completely unsupported by this driver at the moment. [1]
  For Intel eMMC controllers, taking the embedded slot type into account
  obsoltes setting SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE so remove these quirk
  entries.
- Hide the 1.8 V VDD capability when the slot is detected as non-embedded,
  as the SDHCI specification explicitly states that 1.8 V VDD is applicable
  to embedded slots only. [2]
- Define some easy bits of the SDHCI specification v4.20. [3]
- Don't leak bus_dma(9) resources in failure paths of sdhci_init_slot().

Obtained from:	DragonFlyBSD 65704a46 [1], 7ba10b88 [2], 0df14648 [3]
2017-07-26 22:04:23 +00:00
marius
398d5fc6af o Add support for eMMC HS200 and HS400 bus speed modes at 200 MHz to
sdhci(4), mmc(4) and mmcsd(4). For the most part, this consists of:
  - Correcting and extending the infrastructure for negotiating and
    enabling post-DDR52 modes already added as part of r315598. In
    fact, HS400ES now should work as well but hasn't been activated
    due to lack of corresponding hardware.
  - Adding support executing standard SDHCI initial tuning as well
    as re-tuning as required for eMMC HS200/HS400 and the fast UHS-I
    SD card modes. Currently, corresponding methods are only hooked
    up to the ACPI and PCI front-ends of sdhci(4), though. Moreover,
    sdhci(4) won't offer any modes requiring (re-)tuning to the MMC/SD
    layer in order to not break operations with other sdhci(4) front-
    ends. Likewise, sdhci(4) now no longer offers modes requiring the
    set_uhs_timing method introduced in r315598 to be implemented/
    hooked up (previously, this method was used with DDR52 only, which
    in turn is only available with Intel controllers so far, i. e. no
    such limitation was necessary before). Similarly for 1.2/1.8 V VCCQ
    support and the switch_vccq method.
  - Addition of locking to the IOCTL half of mmcsd(4) to prevent races
    with detachment and suspension, especially since it's required to
    immediately switch away from RPMB partitions again after an access
    to these (so re-tuning can take place anew, given that the current
    eMMC specification v5.1 doesn't allow tuning commands to be issued
    with a RPMB partition selected). Therefore, the existing part_mtx
    lock in the mmcsd(4) softc is additionally renamed to disk_mtx in
    order to denote that it only refers to the disk(9) half, likewise
    for corresponding macros.

  On the system where the addition of DDR52 support increased the read
  throughput to ~80 MB/s (from ~45 MB/s at high speed), HS200 yields
  ~154 MB/s and HS400 ~187 MB/s, i. e. performance now has more than
  quadrupled compared to pre-r315598.

  Also, with the advent of (re-)tuning support, most infrastructure
  necessary for SD card UHS-I modes up to SDR104 now is also in place.
  Note, though, that the standard SDHCI way of (re-)tuning is special
  in several ways, which also is why sending the actual tuning requests
  to the device is part of sdhci(4). SDHCI implementations not following
  the specification, MMC and non-SDHCI SD card controllers likely will
  use a generic implementation in the MMC/SD layer for executing tuning,
  which hasn't been written so far, though.

  However, in fact this isn't a feature-only change; there are boards
  based on Intel Bay Trail where DDR52 is problematic and the suggested
  workaround is to use HS200 mode instead. So far exact details are
  unknown, however, i. e. whether that's due to a defect in these SoCs
  or on the boards.

  Moreover, due to the above changes requiring to be aware of possible
  MMC siblings in the fast path of mmc(4), corresponding information
  now is cached in mmc_softc. As a side-effect, mmc_calculate_clock(),
  mmc_delete_cards(), mmc_discover_cards() and mmc_rescan_cards() now
  all are guaranteed to operate on the same set of devices as there no
  longer is any use of device_get_children(9), which can fail in low
  memory situations. Likewise, mmc_calculate_clock() now longer will
  trigger a panic due to the latter.

o Fix a bug in the failure reporting of mmcsd_delete(); in case of an
  error when the starting block of a previously stored erase request
  is used (in order to be able to erase a full erase sector worth of
  data), the starting block of the newly supplied bio_pblkno has to be
  returned for indicating no progress. Otherwise, upper layers might
  be told that a negative number of BIOs have been completed, leading
  to a panic.

o Fix 2 bugs on resume:
  - Things done in fork1(9) like the acquisition of an SX lock or the
    sleepable memory allocation are incompatible with a MTX_DEF taken.
    Thus, mmcsd_resume() must not call kproc_create(9), which in turn
    uses fork1(9), with the disk_mtx (formerly part_mtx) held.
  - In mmc_suspend(), the bus is powered down, which in the typical
    case of a device being selected at the time of suspension, causes
    the device deselection as part of the bus acquisition by mmc(4) in
    mmc_scan() to fail as the bus isn't powered up again before later
    in mmc_go_discovery(). Thus, power down with the bus acquired in
    mmc_suspend(), which will trigger the deselection up-front.

o Fix a memory leak in mmcsd_ioctl() in case copyin(9) fails. [1]

o Fix missing variable initialization in mmc_switch_status(). [2]

o Fix R1_SWITCH_ERROR detection in mmc_switch_status(). [3]

o Handle the case of device_add_child(9) failing, for example due to
  a memory shortage, gracefully in mmc(4) and sdhci(4), including not
  leaking memory for the instance variables in case of mmc(4) (which
  might or might not fix [4] as the latter problem has been discovered
  independently).

o Handle the case of an unknown SD CSD version in mmc_decode_csd_sd()
  gracefully instead of calling panic(9).

o Again, check and handle the return values of some additional function
  calls in mmc(4) instead of assuming that everything went right or mark
  non-fatal errors by casting the return value to void.

o Correct a typo in the Linux IOCTL compatibility; it should have been
  MMC_IOC_MULTI_CMD rather than MMC_IOC_CMD_MULTI.

o Now that we are reaching ever faster speeds (more improvement in this
  regard is to be expected when adding ADMA support to sdhci(4)), apply
  a few micro-optimizations like predicting mmc(4) and sdhci(4) debugging
  to be off or caching erase sector and maximum data sizes as well support
  of block addressing in mmsd(4) (instead of doing 2 indirections on every
  read/write request for determining the maximum data size for example).

Reported by:	Coverity
CID:		1372612 [1], 1372624 [2], 1372594 [3], 1007069 [4]
2017-07-23 16:11:47 +00:00
imp
898d1917b8 Better contain MMCCAM parts of this file
Remove some useless to the general user debugs
Put debugs under sdhci_debug.
Fix some style(9) regressions

Submitted by: marius@
2017-07-10 03:38:17 +00:00
imp
21a75f779f Back out enabling the card interrupt detection bit. It is not ready to
commit.

Noticed by: marius@
2017-07-09 20:49:02 +00:00
imp
a87c7a85be An MMC/SD/SDIO stack using CAM
Implement the MMC/SD/SDIO protocol within a CAM framework. CAM's
flexible queueing will make it easier to write non-storage drivers
than the legacy stack. SDIO drivers from both the kernel and as
userland daemons are possible, though much of that functionality will
come later.

Some of the CAM integration isn't complete (there are sleeps in the
device probe state machine, for example), but those minor issues can
be improved in-tree more easily than out of tree and shouldn't gate
progress on other fronts. Appologies to reviews if specific items
have been overlooked.

Submitted by: Ilya Bakulin
Reviewed by: emaste, imp, mav, adrian, ian
Differential Review: https://reviews.freebsd.org/D4761

merge with first commit, various compile hacks.
2017-07-09 16:57:24 +00:00
marius
042a243978 Correct a typo in the comment part of r320577, later on copied into
the commit message; as actually implemented, the intent is to retry
up to 2 ms for controllers to enable bus power.
Noticed by: ian@, rgrimes@

Additional note: Among others, the problem addressed by r320577 is
the APL32 ("Storage Controllers May Not Be Power Gated") erratum.
Hopefully, along with r318282, r320577 works around the remaining
problems seen with Intel Apollo Lake eMMC and SDXC controllers.
2017-07-03 20:47:32 +00:00
marius
60148c226e Retry up to 20 ms to enable bus power as at least with some Intel
SDHCI/eMMC controllers the first attempt after a D3 to D0 transition,
i. e. when the firmware has put the devices into D3 state before,
can fail.
2017-07-02 19:13:01 +00:00
ivadasz
1363ab7323 Fix typo in Driver Type A/C/D capability checks in sdhci.
Use the SDHCI_CAN_DRIVE_TYPE_A/_C/_D masks to check for Driver Type support,
instead of using the SDHCI_CTRL2_DRIVER_TYPE_A/_C/_D values which are meant
for setting the Driver Type in the HOST_CONTROL2 register.

Approved by:	adrian (mentor), jmcneill
Differential Revision:	https://reviews.freebsd.org/D10999
2017-05-31 19:20:27 +00:00
loos
6eed58e1e7 Add the Marvell SDHCI controller to the list of supported devices in
sdhci_fdt.

Enable the SDHCI controller, bus and devices on ARMADA38X kernel.

Tested on:	ClearFog Pro
Reviewed by:	Marcin Wojtas <mw at semihalf.com>
Sponsored by:	Rubicon Communications, LLC (Netgate)
Differential Revision:	https://reviews.freebsd.org/D10606
2017-05-16 05:10:15 +00:00
marius
e16f2fe291 - Unlike as in the PCI case, when attached to ACPI, Intel Bay Trail
and Braswell eMMC and SDXC controllers share the same IDs. Like in
  the PCI case, Braswell eMMC needs the SDHCI_QUIRK_DATA_TIMEOUT_1MHZ
  quirk (see r311794 for the corresponding change to the sdhci(4) PCI
  PCI front-end), though. However, due to the shared ACPI IDs, this
  is trickier to do.
- Intel Apollo Lake eMMC and SDXC controllers are affected by the
  APL18 ("Using 32-bit Addressing Mode With SD/eMMC Controller May
  Lead to Unpredictable System Behavior") silicon bug [1]. When this
  erratum hits, typically both SDHCI and XHCI controllers wedge.
  According to Intel, using ADMA2 with 64-bit addressing and 96-bit
  descriptors serves as a workaround. Until such times when sdhci(4)
  has ADMA2 support, flag DMA as broken for affected interfaces.
  This turns out to work around the problem, too, at the cost of
  performance.
- In the sdhci(4) ACPI front-end, probe the Intel Apollo Lake eMMC
  and SDXC controllers, too.

1: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/pentium-celeron-n-series-j-series-datasheet-spec-update.pdf
2017-05-14 21:33:01 +00:00
loos
e0630b81d4 Add a new SDHCI quirk, SDHCI_QUIRK_BROKEN_AUTO_STOP, to workaround
controllers that do not support or have broken ACMD12 implementations.

Reviewed by:	jmcneill
Obtained from:	NetBSD
MFC after:	2 weeks
Sponsored by:	Rubicon Communications, LLC (Netgate)
Differential Revision:	https://reviews.freebsd.org/D10602
2017-05-09 19:01:57 +00:00
loos
ae25145e58 Add support for the no-1-8-v and wp-inverted properties in generic SDHCI
FDT glue.

MFC after:	2 weeks
Sponsored by:	Rubicon Communications, LLC (Netgate)
2017-05-04 18:56:11 +00:00
jhibbits
4f8f5b41d0 Use the newly added mpc85xx_get_system_clock()
Simplify the platform clock acquisition by using the new helper function.
2017-04-01 22:35:03 +00:00
marius
409a575ad0 o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and
mmc(4). For the most part, this consists of support for:
  - Switching the signal voltage (VCCQ) to 1.8 V or (if supported
    by the host controller) to 1.2 V,
  - setting the UHS mode as appropriate in the SDHCI_HOST_CONTROL2
    register,
  - setting the power class in the eMMC device according to the
    core supply voltage (VCC),
  - using different bits for enabling a bus width of 4 and 8 bits
    in the the eMMC device at DDR or higher timings respectively,
  - arbitrating timings faster than high speed if there actually
    are additional devices on the same MMC bus.

  Given that support for DDR52 is not denoted by SDHCI capability
  registers, availability of that timing is indicated by a new
  quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
  controllers so far. Generally, what it takes for a sdhci(4)
  front-end to enable support for DDR52 is to hook up the bridge
  method mmcbr_switch_vccq (which especially for 1.2 V signaling
  support is chip/board specific) and the sdhci_set_uhs_timing
  sdhci(4) method.

  As a side-effect, this change also fixes communication with
  some eMMC devices at SDR high speed mode with 52 MHz due to
  the signaling voltage and UHS bits in the SDHCI controller no
  longer being left in an inappropriate state.

  Compared to 52 MHz at SDR high speed which typically yields
  ~45 MB/s with the eMMC chips tested, throughput goes up to
  ~80 MB/s at DDR52.

  Additionally, this change already adds infrastructure and quite
  some code for modes up to HS400ES and SDR104 respectively (I did
  not want to add to much stuff at a time, though). Essentially,
  what is still missing in order to be able to activate support
  for these latter is is support for and handling of (re-)tuning.

o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
  hw.sdhci.quirk_set, which (when hooked up in the front-end)
  allow to set/clear sdhci(4) quirks for debugging and testing
  purposes. However, especially for SDHCI controllers on the
  PCI bus which have no specific support code so far and, thus,
  are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
  allows for setting the necessary quirks (if required).

o In mmc(4), check and handle the return values of some more
  function calls instead of assuming that everything went right.
  In case failures actually are not problematic, indicate that
  by casting the return value to void.

Reviewed by:	jmcneill
2017-03-19 23:27:17 +00:00
marius
bb0bcdd7a4 Again, fixes regarding style(4), to comments, includes and unused
parameters.
2017-03-17 22:57:37 +00:00
marius
f3c5ded4e7 - Adds macros for the content of SDHCI_ADMA_ERR and SDHCI_HOST_CONTROL2
registers.
- Add slot type capability bits. These bits should allow recognizing
  removable card slots, embedded cards and shared buses (shared bus
  supposedly is always comprised of non-removable cards).
- Dump CAPABILITIES2, ADMA_ERR, HOST_CONTROL2 and ADMA_ADDRESS_LO
  registers in sdhci_dumpregs().
- The drive type support flags in the CAPABILITIES2 register are for
  drive types A,C,D, drive type B is the default setting (value 0) of
  the drive strength field in the SDHCI_HOST_CONTROL2 register.

Obtained from:	DragonFlyBSD (9e3c8f63, 455bd1b1)
2017-03-16 22:42:17 +00:00