about uss820dci_odevd being unused, by adding it to the part that
handles getting descriptors.
Reported by: loos
Reviewed by: hselasky
MFC after: 3 days
should fix DMA descriptor caching issues seen with the EHCI controller
found in Google Chromebook C720 during removal and insertion of USB
devices.
MFC after: 1 week
Reported by: Matthew Dillon at DragonFlyBSD
to check the status property in their probe routines.
Simplebus used to only instantiate its children whose status="okay"
but that was improper behavior, fixed in r261352. Now that it doesn't
check anymore and probes all its children; the children all have to
do the check because really only the children know how to properly
interpret their status property strings.
Right now all existing drivers only understand "okay" versus something-
that's-not-okay, so they all use the new ofw_bus_status_okay() helper.
controller found in the MBP2013 has been observed to not work properly
unless this operation is performed.
MFC after: 1 week
Tested by: Huang Wen Hui <huanghwh@gmail.com>
value. The "Intel Lynx Point" XHCI controller found in the MBP2013 has
been observed to not always set the event interrupt bit while there
are events to consume in the event ring.
MFC after: 1 week
Tested by: Huang Wen Hui <huanghwh@gmail.com>
Some Intel XHCI controlles timeout processing so-called "TRBs" when
the final LINK TRB of a so-called "TD" has the CHAIN-BIT set.
MFC after: 1 week
Tested by: glebius @
receiving Zero Length Packets, ZLPs. See comment in code for more
information.
MFC after: 1 week
Reported by: Kohji Okuno <okuno.kohji@jp.panasonic.com>
shifts into the sign bit. Instead use (1U << 31) which gets the
expected result.
This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.
A similar change was made in OpenBSD.
Discussed with: -arch, rdivacky
Reviewed by: cperciva
than one unit with four busses attached to it. This allows us to use
existing fdt data which describes separate devices with separate resources.
It also allows any combination of the units to be en/disabled in the
board dts files.
Adjust our dts code to match what's used by linux and u-boot now that
we're structured to do so.
Document lots of interesting stuff learned whiling doing this with a big
comment block in the driver, so I don't have to re-learn it for the next
round of changes.
and not 8-bit. Fix support for isochronous transfers in USB host mode.
Fix a whitespace while at it.
MFC after: 1 week
Reported by: SAITOU Toshihide <toshi@ruby.ocn.ne.jp>
PR: usb/181987
routing if we get certain errors. Poll for command completion upon
command timeouts. The XHCI error events might not generate interrupts.
MFC after: 1 week
Reported by: Daniel Gerzo <danger@rulez.sk>, Antonis Anastasiadis <anastasiadis@datalive.gr>
PR: usb/181159
Approved by: re (gjb)
IMAN register to clear the pending interrupt status bits. This patch
tries to solve problems seen on the MacBook Air, as reported by
Johannes Lundberg <johannes@brilliantservice.co.jp>
MFC after: 1 week
The Block Event Interrupts, BEI, feature does not
work like expected with the Renesas XHCI chipsets.
Revert feature.
While at it correct the TD SIZE computation in
case of Zero Length Packet, ZLP, in the end of a
multi frame USB transfer.
MFC after: 1 week
PR: usb/180726
1) Only multi-TD isochronous transfers should use NORMAL
type after specific type as per XHCI specification.
2) BEI bit is only available in NORMAL and ISOCHRONOUS
TRB types. Don't use this bit for other types to avoid
hardware asserts. Reserved bits should be don't care
though ...
MFC after: 1 week
PR: usb/179342
the regular interrupt handler is not working properly or
in case of MSI interrupts which are not yet supported.
Remove interrupt setup code for FreeBSD versions older
than 700031.
MFC after: 1 week
PR: usb/179342
controller hardware most likely present on UHCI chipsets aswell. The
bug manifests itself when issuing isochronous transfers and bulk
transfers towards the same device simultaneously. From time to time it
happens that either the completion IRQ was missing or that the
completion IRQ was happening before the ITD/SITD was completely
written back to memory. The workaround assumes that double buffered
isochronous transfers are used, and that a second interrupt is
generated at the beginning of the next isochronous transfer to
complete the previous one. Possibly skipping the interrupt at the last
isochronous frame is possible, but will then break single buffered
isochronous transfers. For now we can live with some extra interrupts.
MFC after: 1 week
