baseline subtraction, and are very temperature sensitive, so would slowly
drift out of a calibrated state when under load. Escape this by taking
the last frame before we decide that the pad is idle as a finger-free
baseline.
Tested on: iBook G4
long as I remember, and completely superseded by better maintained umass(4).
It's main idea was to optionally avoid CAM dependency for such devices, but
with move ATA to CAM, it is not actual any more.
No objections: hselasky@, thompsa@, arch@
message has been printed is enough to get someones attention. Also remove the
line number for DPRINTF/DPRINTFN, it already prints the funtion name and a
unique message.
- fix a system deadlock on process exit when the sample buffer
is full (pmclog_loop blocked in fo_write) and pmcstat exit.
Reviewed by: jkoshy
MFC after: 3 weeks
bits on seems to confuse hardware TX engine.
- For 350 chips, set TX desc's buffer physical address before turning on the
TX desc valid bit.
Submitted by: Jeremy O'Brien obrien654j | gmail, sephe
Obtained from: DragonFly BSD
- Extend XPT-SIM transfer settings control API. Now it allows to report to
SATA SIM number of tags supported by each device, implement ATA mode and
SATA revision negotiation for both SATA and PATA SIMs.
- Make ahci(4) and siis(4) to use submitted maximum tag number, when
scheduling requests. It allows to support NCQ on devices with lower tags
count then controller supports.
- Make PMP driver to report attached devices connection speeds.
- Implement ATA mode negotiation between user settings, device and
controller capabilities.
Tx/Rx/Rx return ring such that large part of status block was not
used at all. All bge(4) controllers except BCM5700 AX/BX has a
feature to control the size of status block. So use minimum status
block size allowed in controller. This reduces number of DMAed
status block size to 32 bytes from 80 bytes.
seem to require a special firmware to use TSO. But the firmware is
not available to FreeBSD and Linux claims that the TSO performed by
the firmware is slower than hardware based TSO. Moreover the
firmware based TSO has one known bug which can't handle TSO if
ethernet header + IP/TCP header is greater than 80 bytes. The
workaround for the TSO bug exist but it seems it's too expensive
than not using TSO at all. Some hardwares also have the TSO bug so
limit the TSO to the controllers that are not affected TSO issues
(e.g. 5755 or higher).
While I'm here set VLAN tag bit to all descriptors that belengs to
a frame instead of the first descriptor of a frame. The datasheet
is not clear how to handle VLAN tag bit but it worked either way in
my testing. This makes it simplify TSO configuration a little bit.
Big thanks to davidch@ who sent me detailed TSO information.
Without this I was not able to implement it.
Tested by: current
have a DMA bug when buffer address crosses a multiple of the 4GB
boundary(e.g. 4GB, 8GB, 12GB etc). Limit DMA address to be within
4GB address for these controllers. The second DMA bug limits DMA
address to be within 40bit address space. This bug applies to
BCM5714 and BCM5715 and 5708(bce(4) controller). This is not
actually a MAC controller bug but an issue with the embedded PCIe
to PCI-X bridge in the device. So for BCM5714/BCM5715 controllers
also limit the DMA address to be within 40bit address space.
Special thanks to davidch@ who gave me detailed errata information.
I think this change will fix long standing bge(4) instability
issues on systems with more than 4GB memory.
Reviewed by: davidch
PCI flush to get correct status block update. Add an optimized
interrupt handler that is activated for MSI case. Actual interrupt
handling is done by taskqueue such that the handler does not
require driver lock for Rx path. The MSI capable bge(4) controllers
automatically disables further interrupt once it enters interrupt
state so we don't need PIO access to disable interrupt in interrupt
handler.
update and then clear status block. Previously it used to access
these index without synchronization which may cause problems when
bounce buffers are used. Also add missing bus_dmamap_sync(9) in
polling handler. Since we now update status block in driver, adjust
bus_dmamap_sync(9) for status block.
checking IFF_DRV_RUNNING and IFF_DRV_OACTIVE flags. Also if we
have less than 16 free send BDs set IFF_DRV_OACTIVE and try it
later. Previously bge(4) used to reserve 16 free send BDs after
loading dma maps but hardware just need one reserved send BD. If
prouder index has the same value of consumer index it means the Tx
queue is empty.
While I'm here check IFQ_DRV_IS_EMPTY first to save one lock
operation.
directly access them at fixed address. While I'm here don't touch
other bits of PCIe device control register except max payload size.
Reviewed by: marius
Binary divider value 10 specified in datasheet is not a hex 0x10.
UDMA2 should be 33/2 instead of 66/4, which is documented as reverved,
UDMA4 should be 66/2 instead of 66/4, which is definitely wrong.
controller also has support for IP/TCP checksum offloading for Rx
path. But I failed to find to way to enable Rx MAC to compute the
checksum of received frames.
both big-endian and little-endian format in descriptors for Rx path
but I couldn't find equivalent feature in Tx path. So just stick to
little-endian for now.
directly access them at fixed address. Frequently the register
offset could be changed if additional PCI capabilities are added to
controller.
One odd thing is ET_PCIR_L0S_L1_LATENCY register. I think it's PCIe
link capabilities register but the location of the register does
not match with PCIe capability pointer + offset. I'm not sure it's
shadow register of PCIe link capabilities register.
if_watchdog and if_timer.
- Fix some issues in detach for sn(4), ste(4), and ti(4). Primarily this
means calling ether_ifdetach() before anything else.
- Overhaul the locking to avoid recursion and add missing locking in a few
places.
- Don't schedule a task to call vge_start() from contexts that are safe to
call vge_start() directly. Just invoke the routine directly instead
(this is what all of the other NIC drivers I am familiar with do). Note
that vge(4) does not use an interrupt filter handler which is the primary
reason some other drivers use tasks.
- Add a new private timer to drive the watchdog timer instead of using
if_watchdog and if_timer.
- Fixup detach by calling ether_ifdetach() before stopping the interface.
just two different attachments (EISA and PCI) to a single driver.
- Add real locking. Previously these drivers only acquired their lock
in their interrupt handler or in the ioctl routine (but too broadly in
the latter). No locking was used for the stack calling down into the
driver via if_init() or if_start(), for device shutdown or detach. Also,
the interrupt handler held the driver lock while calling if_input(). All
this stuff should be fixed in the locking changes.
- Really fix these drivers to handle if_alloc(). The front-end attachments
were using if_initname() before the ifnet was allocated. Fix this by
moving some of the duplicated logic from each driver into pdq_ifattach().
While here, make pdq_ifattach() return an error so that the driver just
fails to attach if if_alloc() fails rather than panic'ing. Also, defer
freeing the ifnet until the driver has stopped using it during detach.
- Add a new private timer to drive the watchdog timer.
- Pass the softc pointer to the interrupt handlers instead of the device_t
so we can avoid the use of device_get_softc() and to better match what
other drivers do.
auto-negotiation. To make this simpler and easier to understand I have
split this out into two separate timers. One just manages the auto-neg
side of things and one is a transmit watchdog. Neither uses if_watchdog.
- Call ether_ifdetach() at the start of detach.
- Add a missing callout_drain() to detach.
- Hook into the stats timer and use that to drive the transmit watchdog
instead of using if_watchdog.
- Run the stats timer every second to match other drivers instead of every
other second.
- Remove dubious callout handling that stopped the timer only to start it
again while holding the driver lock without dropping it in between the
stop and the start.
reliable on some Marvell PHYs. If msk(4) know it still does not
have established link check whether msk(4) missed the link state
change by looking into polled link state.
Reported by: Mel Flynn < mel.flynn+fbsd.current <> mailing.thruhere dot net >,
Gleb Kurtsou <gleb.kurtsou <> gmail dot com >
Tested by: Gleb Kurtsou <gleb.kurtsou <> gmail dot com >
the transmit watchdog. These drivers already used a private timer when
compiled to use Netgraph. This change just makes them always use the
private timer. Note that these drivers do not compile and are disconnected
from the build due to TTY changes.
if_watchdog and if_timer. The driver already contained an optional stats
timer that individual attachments could use to provide a 'tick' event. The
stats timer only ran if the tick function pointer was non-NULL and the
attachment's tick routine had to call callout_reset(), etc. Now the driver
always schedules a stat timer and manages the callout_reset() internally.
This timer is used to drive the watchdog and will also call the attachment's
'tick' handler if one is provided.
Tested by: WATANABE Kazuhiro
and Marvell handled. Instead of trying to attach two different drivers to
single device, wrapping each call, make one of them (atajmicron, atamarvell)
attach do device solely, but create child device for AHCI driver,
passing it all required resources. It is quite easy, as none of
resources are shared, except IRQ.
As result, it:
- makes drivers operation more independent and straitforward,
- allows to use new ahci(4) driver with such devices, adding support for
new features, such as PMP and NCQ, same time keeping legacy PATA support,
- will allow to just drop old ataahci driver, when it's time come.
errors. So far 3 different classes are present (correctable,
uncorrectable and fatal) but more can be added easilly.
Obtained from: Sandvine Incorporated
Reviewed by: emase, gibbs
Sponsored by: Sandvine Incorporated
MFC: 2 weeks
These controllers provide combination of AHCI for SATA and legacy
PCI ATA for PATA. Use same solution as used for JMicron controllers.
Add IDs of Marvell 88SX6102, 88SX6111. 88SX6141 alike controllers
Right now syscons(4) uses a cons25-style terminal emulator. The
disadvantages of that are:
- Little compatibility with embedded devices with serial interfaces.
- Bad bandwidth efficiency, mainly because of the lack of scrolling
regions.
- A very hard transition path to support for modern character sets like
UTF-8.
Our terminal emulation library, libteken, has been supporting
xterm-style terminal emulation for months, so flip the switch and make
everyone use an xterm-style console driver.
I still have to enable this on i386. Right now pc98 and i386 share the
same /etc/ttys file. I'm not going to switch pc98, because it uses its
own Kanji-capable cons25 emulator.
IMPORTANT: What to do if things go wrong (i.e. graphical artifacts):
- Run the application inside script(1), try to reduce the problem and
send me the log file.
- In the mean time, you can run `vidcontrol -T cons25' and `export
TERM=cons25' so you can run applications the same way you did before.
You can also build your kernel with `options TEKEN_CONS25' to make all
virtual terminals use the cons25 emulator by default.
Discussed on: current@
