Reduce the use of local copies of switch register data.
The switch now works with the upstream dsa node (i.e. the upstream DTS).
Tested on: ClearFog Pro (88E6176), SG-3100 (88E6141)
Sponsored by: Rubicon Communications, LLC (Netgate)
r319886 ("Add the initial support for the Marvell 88E6141
and 88E6341 switches.") unveiled a problem with possible
multiple lock creation. Move its initialization
to the driver attach and for obtaining the switch ID
create a temprorary one, which is immediately destroyed
after the check.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Marcin Wojtas <mw@semihalf.com>
Obtained from: Semihalf
Right now the driver only supports port VLANs, so make sure
etherswitch_getinfo() return the proper switch capabilities.
Handle the cases where not all ports are in use (that will also require
etherswitch cooperation).
Sponsored by: Rubicon Communications, LLC (Netgate)
Tested on WZR-HP-G301NH(RTL8366RB) and WZR-HP-G300NH(RTL8366SR).
Submitted by: Hiroki Mori <yamori813@yahoo.co.jp>
Differential Revision: https://reviews.freebsd.org/D10740
e6000sw family automatically reflects PHY status in each port's registers.
Therefore it is not necessary to do a full PHY polling squence, which
results in much quicker operation and much less significant usage of
the SMI bus.
Care must be taken that the resulting ifmedia_active is identical to
what the PHY will compute, or gratuitous link status changes will
occur whenever the PHYs update function is called.
This patch implements above improvement. On the occasion set a pointer to
the proc structure to be part of software context instead of being
a global variable.
Submitted by: Marcin Wojtas <mw@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: loos
Differential revision: https://reviews.freebsd.org/D10714
Hitherto implementation of PHY polling resulted in a risk of an
endless loop and very high occupation of the SMI bus. Improve the
operation by limiting the polling tries and adding sleepable
pause.
Submitted by: Marcin Wojtas <mw@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: loos
Differential revision: https://reviews.freebsd.org/D10713
Malloc should always return something when M_WAITOK flag is used,
but keep this code and change flag to M_NOWAIT as it is under a lock
(allows for possible future change). Free ifnet structure to avoid
memory leak on failure.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: loos
Differential revision: https://reviews.freebsd.org/D10711
Add workaround mii access because of rt1310 is hang up on etherswitch mii poll.
And FDT away on arm platform.
Tested:
* wzr2-g300n
Submitted by: Hiroki Mori <yamori813@yahoo.co.jp>
Reviewed by: mizhka
Differential Revision: https://reviews.freebsd.org/D10295
cannot access the GLOBAL2 register directly.
Despite the comment in code (which was misleading), the indirect access is
only used to read the switch CONFIG data from the scrap register and not
for the GLOBAL2 access.
Use the dsa data to define when the switch is in the Multi Chip Addressing
Mode (a even address different than zero).
While here fix a typo.
Sponsored by: Rubicon Communications, LLC (Netgate)
This patch brings 802.1q support for Marvell 88E606x ethernet switches.
Test is done on 88E6065 chip (Aterm WR1200).
Submitted by: Hiroki Mori <yamori813@yahoo.co.jp>
Reviewed by: mizhka
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D10144
arswitch_setled() and a number of _global_setup functions did not acquire the
lock before calling arswitch_modifyreg(). With WITNESS enabled this would
instantly panic.
Discovered on a TPLink-3600:
("panic: mutex arswitch not owned at sys/dev/etherswitch/arswitch/arswitch_reg.c:236")
Reviewed by: adrian, kan
Differential Revision: https://reviews.freebsd.org/D9187
This is Micrel KSZ8995MA driver code. KSZ8995MA uses SPI bus to control.
This code is written & tested on @SRCHACK's ksz8995ma board and FON2100
with gpiospi.
etherswitchcfg support commands: addtag, ingress, striptag, dropuntagged.
Submitted by: Hiroki Mori <yamori813@yahoo.co.jp>
Reviewed by: mizhka, adrian
Approved by: adrian (mentor)
Differential Revision: https://reviews.freebsd.org/D8790
- recognize ports and vlangroups based on DTS file
- support multi-chip addresing mode (required in upcoming
Armada-388-Clearfog support)
- refactor attachment function
Each port in 'dsa' node should have 'vlangroup' property. Otherwise,
e6000sw will fail to attach.
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Konrad Adamczyk <ka@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D7328
it.
Remove bogus wrappers and use the kernel defaults.
While here, use DEVMETHOD_END.
Obtained from: pfSense
MFC after: 2 weeks
Sponsored by: Rubicon Communications, LLC (Netgate)
This patch allows to specify PHY register offset for ukswitch. For instance,
switch MAICREL KS8995XA connected via MDIO to SoC, but PHY register starts
at 1. So hint for this case is: hint.ukswitch.0.phyoffset=1
No change/effect if hint is not set.
Submitted by: Hiroki Mori <yamori813@yahoo.co.jp>
Reviewed by: adrian, mizhka
Approved by: adrian(mentor)
Differential Revision: https://reviews.freebsd.org/D8584
This is Infineon ADM6996FC/M/MX driver code on etherswitch framework.
Support PORT and DOT1Q VLAN.
This code suppose ADM6996FC SDC/SDIO connect to SOC network interface
MDC/MDIO.
This code tested on Netgear WGR614Cv7.
Submitted by: Hiroki Mori <yamori813@yahoo.co.jp>
Reviewed by: adrian, mizhka
Approved by: adrian(mentor)
Differential Revision: https://reviews.freebsd.org/D8495
If MII1 interface is disabled, then enable phy4/mac4.
Submitted by: Hiroki Mori <yamori813@yahoo.co.jp>
Reviewed by: mizhka, adrian
Approved by: adrian (mentor)
Differential Revision: https://reviews.freebsd.org/D6832
Uses of commas instead of a semicolons can easily go undetected. The comma
can serve as a statement separator but this shouldn't be abused when
statements are meant to be standalone.
Detected with devel/coccinelle following a hint from DragonFlyBSD.
MFC after: 1 month
* remove the DEBUG ifdef; defining it is too far reaching throughout
the whole system;
* add a bitmask in the softc for controlling debugging;
* .. enable said debugging as a sysctl;
* add bitmaps for register access, reset and vlans.
TODO:
* Now that the debug statements are configurable, we definitely could
do with more debugging
* Move the debugging into the top-level etherswitch driver and have
sub-drivers obey.
In mediatek etherswitch support, functions mtkswitch_reg_write32_mt7621
and mtkswitch_reg_read32_mt7621 are called without locks held, so
lock assertions fail. Remove the lock assertions.
Sponsored by: Smartcom - Bulgaria AD
Fix issues that crept in with initial import.
Approved by: adrian (mentor)
Sponsored by: Smartcom - Bulgaria AD
Differential Revision: https://reviews.freebsd.org/D6393
This revision introduces basic support for the internal ESW switch found
Ralink/Mediatek SoCs such as RT3050, RT3352, RT5350, MT7628; and GSW
found in MT7620 and MT7621.
It only supports 802.1q VLANs and doesn't support external PHYs at the
moment (only the ones that are built into the switch itself).
Approved by: adrian (mentor)
Sponsored by: Smartcom - Bulgaria AD
Differential Revision: https://reviews.freebsd.org/D6348
The mdio driver interface is generally useful for devices that require
MDIO without the full MII bus interface. This lifts the driver/interface
out of etherswitch(4), and adds a mdio(4) man page.
Submitted by: Landon Fuller <landon@landonf.org>
Differential Revision: https://reviews.freebsd.org/D4606
Add e6000sw driver supporting Marvell 88E6352, 88E6172, 88E6176 switches.
It needs to be attached to mdio interface, exporting SMI access
functionality. e6000sw supports port-based VLAN configuration, per-port
media changing, accessing PHY and switch registers.
e6000sw attaches miibuses and PHY drivers as children. Instead of typical
tick as callout, kthread-based tick is used. This combined with SX locks
allows MDIO read/write calls to sleep. It is expected, because this
hardware requires long delays in SMI read/write procedures, which can not
be handled by busy-waiting.
Reviewed by: adrian
Obtained from: Semihalf
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D3902
I messed up when doing the reset_vlans method - setting vid[0] = 1 here
was making it 'hidden' from configuration (as it needed ETHERSWITCH_VID_VALID
as well) and so there was no way to configure vlangroup0.
In per-port VLAN mode, vlangroup0 is for the CPU port (port0).
Now, it normally wouldn't really matter - the CPU port thus sees
all other ports. However there are two CPU ports on the AR8327 and
so port0 (arge0) was seeing all traffic on port6 (arge1).
If you thus tried to use arge1/port6 for anything (eg a WAN port)
in a bridge group then things would very upset very quickly.
Whilst here, add a comment to remind myself that yes, it'd be nice
if we could specify a boot-time switch config.
Tested:
* AP135 reference platform w/ AR8327N switch
This is slightly different to the other switches - the VLAN table
(VTU) programs in the vlan port mapping /and/ the port config
(tagged, untagged, passthrough, any.)
So:
* Add VTU operations to program the VTU (vlan table)
* abstract out the mirror-disable function so it's .. well, a function.
* setup the port to have a dot1q configuration for dot1q - the
port security is VLAN (not per-port VLAN) and requires an entry
in the VLAN table;
* add set_dot1q / get_dot1q to program the VLAN table;
* since the tagged/untagged ports are now programmed into the VTU,
rather than global - plumb the ports /and/ untagged ports bitmaps
through the arswitch API.
Tested:
* AP135 - QCA9558 SoC + AR8327N switch
All the per-port support is really doing is applying a port visibility
mask to each of the switchports. Everything still look like a single
portgroup (vlan id 1), but the per-port visibility mask is modified.
Whilst I'm here, also add some initial dot1q support - the pvid stuff
is doing the right thing, but it's not useful without the rest of
the VLAN table programming.
It's enough for me to be able to use the LAN/WAN port distinction
on the AP135, where there isn't (for now!) a dedicated PHY for the
"WAN" port.
Tested:
* AP135, QCA9558 SoC + AR8327 switch
* Even though I got the registers around "right", it seems
I'm not tickling the MDIO access correctly for the internal PHY
bus. Some of the switches are fine poking at the external PHY
registers; others aren't. So, enable direct PHY bus access
for the AR8327, and leave the existing code in place for the
others.
* Go and shuffle the register access around. Whilst here,
restore the 2ms delay if changing page.
* Comment out some of the stub printf()s; there's some upcoming
work to add port VLAN support.
Tested:
* AP135 development board
* Carambola2 - AR9331 SoC
I noticed that openwrt/linux does this, citing "instability", so
until they figure out why I'm going to disable it here as well.
Tested:
* QCA AP135 - QCA955x SoC + AR8327 switch.
So, it turns out that the AR8327 has 7 ports internally:
* GMAC0 / external (CPU) MAC0
* GMAC1 / port1 -> GMAC5 / port5: external switch port PHYs
* GMAC6 / external (CPU) MAC1
Now, depending upon how things are wired up, the second CPU port (MAC1)
can be wired to either the switch (port6), or through port5's PHY, bypassing
the GMAC+switch entirely. Ie, it can pretend to be a boring PHY, saving
system designers from having to include a separate PHY for a "WAN" port.
Here's the rub - the AP135 board (QCA955x SoC) hooks up arge0 to
the second CPU port on the AR8327, but it's hooked up as RGMII.
So, in order to hook it up to the rest of the switch, it isn't configured
as a separate PHY - OpenWRT has it setup as connected via RGMII to
GMAC6 and (I'm guessing) it's set to be a WAN port by configuring up
port-based VLANs or something.
Thus, with a port mask of 0x3f, GMAC6 was never allowed to receive traffic
from any other port. It could transmit fine, but not receive anything.
So, now it works enough for me to continue doing board bootstrapping.
Note, this isn't enough to make the QCA955x + AR8327 work - there's
a bunch of uncommitted work to both the platform SoC (interrupt handling,
ethernet, etc) and the ethernet switch (register access space, setup, etc)
that needs to happen. However, this particular change is also relevant to
other SoCs, like the AR934x and AR7161, both of which can be glued to
this switch.
Tested:
* AP135 development board
TODO:
* Figure out whether I can somehow abuse another port mode to have this
be a pass-through PHY, or whether I should just create some more boot
time hints to explicitly set up port-based isolation so this works
in a more useful way by default.
