- Hardcode '8' instead of NBBY in _BITSET_BITS.
- Define a private version of 'howmany' for use in __bitset_words().
- While here, move a few more things out of _bitset.h and _cpuset.h to
bitset.h and cpuset.h, respectively. The only things left in
_bitset.h and _cpuset.h are the bits needed to define a bitset
structure.
Reviewed by: bde, kib (ish)
struct associated with some type defined in enum intr_map_data_type
must have struct intr_map_data on the top of its own definition now.
When such structs are used, correct type and size must be filled in.
There are three such structs defined in sys/intr.h now. Their
definitions should be moved to corresponding headers by follow-up
commits.
While this change was propagated to all INTRNG like PICs,
pic_map_intr() method implementations were corrected on some places.
For this specific method, it's ensured by a caller that the 'data'
argument passed to this method is never NULL. Also, the return error
values were standardized there.
Clocks, GPIO, UART, SD card / eMMC, USB, watchdog, and ethernet are
supported. Note that the A83T contains two clusters of four Cortex-A7
CPUs, and only CPUs in first cluster are started for now.
Tested on a Sinovoip Banana Pi BPI-M3.
The datasheets refer to this controller as EMAC, not to be confused with
the fast ethernet controller (also named EMAC) found in A10/A20 SoCs.
Tested on a BananaPi M3 (A83T), which uses an external RGMII PHY (RTL8211E).
Reviewed by: adrian
Differential Revision: https://reviews.freebsd.org/D6169
Add the needed hardcoded gem5 attachments for the UART there, re-using all
the other bits.
In collaboration with: andrew
Sponsored by: DARPA/AFRL
Reviewed by: andrew
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D6204
In case we do not have an interrupt assignment for the virtual timer,
force the physical timer.
Also skip resource allocation for any timer we do not have an interrupt
assignment for.
In collaboration with: andrew
Submitted by: br ([1] from his gem5 arm64 work)
Sponsored by: DARPA/AFRL
Reviewed by: andrew
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D6203
In case of updating it with a very low value it might expire again
after writing the tval but before updating ctrl. In that case we do
lose the status bit saying that the timer expired and we will consequently
not get an interrupt for it, leaving the timer in a "dead" state.
In order to solve this increase the minimum period with what the timer
can be loaded to something higher.
Found & analysed with: gem5
Debugged with: andrew
Sponsored by: DARPA/AFRL
Reviewed by: andrew
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D6202
implementations. Early in the boot the kernel will use an approximate,
however after the timer has been probed it will switch to a more accurate
implementation.
Reviewed by: manu
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5762
Split ADC driver in two halves: ADC(analog ot digital) and
TSC(touchscreen). Touchscreen driver is fully functional
up to the point of reporting samples. This part will be added
once FreeBSD has API for touchscreen.
Tested on: Beaglebone Black + 4DCAPE-43T
Reviewed by: loos
Differential Revision: https://reviews.freebsd.org/D5847
On ARM, we can directly switch between translation tables only when
the size of the mapping for any given virtual address is the same in
the old and new translation tables. The load of new TTB and subsequent
TLB flush is not atomic operation. So speculative page table walk can
load TLB entry from new mapping while rest of TLB entries are still the
old ones. In worst case, this can lead to situation when TLB cache can
contain multiple matching TLB entries. One (from old mapping) L2 entry
for VA + 4k and one (from new mapping) L1 entry for VA.
Thus, we must switch to kernel pmap translation table as intermediate
mapping because all sizes of these (old pmap and kernel pmap) mappings
are same (or unmapped). The same is true for switch from kernel pmap
translation table to new pmap one.
Set MMC_CAP_4_BIT_DATA and MMC_CAP_8_BIT_DATA based on the "bus-width"
DT property and reduce maximum bus frequency from 52MHz to 50MHz to match
the capabilities of the clock provider.
Tested on a BananaPi BPI-M3 (A83T).
Such situation is defined as UNPREDICTABLE by arm arm manual.
This patch fixes all explicit TLB fetches which could cause this issue
and speculative TLB fetches for sections mapped in user address space.
Speculative TLB fetches for sections mapped in kernel address space are
not fixed yet as the break-before-make approach must be implemented for
kernel mappings too. This means that promoted/demoted section will be
unmapped for a while. Either kernel stack the promotion/demotion is
being done on or L1 page table(s) which must be modified may be mapped
by this section. Thus the fix will not be so simple like for userland
mappings.
The issue was detectable only on Cortex-A8 platforms and only very
rarely. It was reported few times. First, it was by Mikael Urankar
in June 2015. He helped to identify the mechanism of this issue, but
we were not sure how to fix it correctly until now.
PR: 208381
Reported by: Mikael Urankar (mikael.urankar at gmail.com)
Reviewed by: kib
and R/W emulation aborts under pmap lock.
There were two reasons for using of atomic operations:
(1) the pmap code is based on i386 one where they are used,
(2) there was an idea that access and R/W emulation aborts should be
handled as quick as possible, without pmap locking.
However, the atomic operations in i386 pmap code are used only because
page table entries may be modified by hardware. At the beginning, we
were not sure that it's the only reason. So even if arm hardware does
not modify them, we did not risk to not use them at that time. Further,
it turns out after some testing that using of pmap lock for access and
R/W emulation aborts does not bring any extra cost and there was no
measurable difference. Thus, we have decided finally to use pmap lock
for all operations on page table entries and so, there is no reason for
atomic operations on them. This makes the code cleaner and safer.
This decision introduce a question if it's safe to use pmap lock for
access and R/W emulation aborts. Anyhow, there may happen two cases in
general:
(A) Aborts while the pmap lock is locked already - this should not
happen as pmap lock is not recursive. However, under pmap lock only
internal kernel data should be accessed and such data should be mapped
with A bit set and NM bit cleared. If double abort happens, then
a mapping of data which has caused it must be fixed.
(B) Aborts while another lock(s) is/are locked - this already can
happen. There is no difference here if it's either access or R/W
emulation abort, or if it's some other abort.
Reviewed by: kib
(PL1) and unprivileged (PL0) read/write access. As cp15 virtual to
physical address translation operations are used, interrupts must be
disabled to get consistent result when they are called.
These functions should be used only in very specific occasions like
during abort handling or kernel debugging. One of them is going to be
used in pmap_fault(). However, complete function set is added. It cost
nothing, as they are inlined.
While here, fix comment of #endif.
Reviewed by: kib
rounddown2 tends to produce longer lines than the original code
and when the code has a high indentation level it was not really
advantageous to do the replacement.
This tries to strike a balance between readability using the macros
and flexibility of having the expressions, so not everything is
converted.
bcm2835_mbox_fb_init sets configuration so SET_VIRTUAL_OFFSET should be used
instead of GET_VIRTUAL_OFFSET
Submitted by: Sylvain Garrigues <sylvain@sylvaingarrigues.com>
VideoCore reports garbage in viewport geometry fields unless
viewport was set previously by earlier stage boot loader. So
when booting FreeBSD kernel directly from VideoCore's start.elf
framebuffer intialization fails due to invalid vxres, vyres
values. Make sure we request viewport to be equal to physical
resolution
Submitted by: Sylvain Garrigues <sylvain@sylvaingarrigues.com>
write to the End of Interrupt (EOI) register before handling the interrupt.
This should be a noop as it will be set for all edge triggered interrupts,
however this will not be the case for MSI interrupts. These are also edge
triggered, however we should not write to the EOI register until later in
arm_gic_pre_ithread.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
support MSI and MSI-X interrupts, however intrng needs updates before this
can happen.
For now we just attach the driver until the MSI API is ready.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D5950
- Pre-buffer audio data to VideoCore so there are no audible glitches when
driver is too late to provide samples
- Start actual playback when there is some prebuffered audio,
it fixes audible noisy click in the beginning of playback
- Use #defines instead of hardcoded values where appropriate
- Fix copy-pasted comment
PR: 208678
value that can't ever be in an inconsistant intermediate state even when
some other thread is in the middle of writing the value/register.
Locking of the hardware remains in the few places that do r-m-w operations.
Locking of metadata access is restricted to places using memcpy or sprintf
to modify the metadata.
