2351 Commits

Author SHA1 Message Date
ian
6765240e8d Replace many pasted identical definitions of cpu_initclocks() with a common
implementation in arm/machdep.c.  Most arm platforms either don't need to
do anything, or just need to call the standard eventtimer init routines.
A generic implementation that does that is now provided via weak linkage.
Any platform that needs to do something different can provide a its own
implementation to override the generic one.
2014-02-26 22:06:10 +00:00
ian
509a9dbc3f Minor tweaks to the imx GPT timer...
- Don't use spaces or dots in the eventtimer or timecounter names.
   They turn into sysctl node names, and it's just confusing.
 - Use comparator #3 instead of #1 for one-shot events.  There's an
   extra 1-cycle penalty in the hardware for accessing the registers
   for comparator 1, no point in paying that penalty.
 - Lower the quality of the eventtimer from 1000 to 800, because the
   device can't support PERCPU timers and some other device in the system
   may be able to provide that.
2014-02-26 18:29:14 +00:00
br
ed49704845 - Pin configuration is a complete iomux register now and includes
drive strength, pull mode, mux mode, speed, etc.
- Add i2c devices to the tree
- Add IPG clock
2014-02-25 17:02:11 +00:00
ian
0245f95433 Invalidate the SCU cache tag ram on all 4 cores, not just 1-3. I misread
Juergen's original code, it was doing all 4 cores.  Also remove the L2
cache invalidate operation, this code runs before L2 is activated.
2014-02-25 15:22:40 +00:00
br
8a2388e536 Add support for Quartz Module.
Quartz is a tiny module utilized Freescale VF6xx
system-on-chip and development kit produced by
Device Solutions.

Quartz is available in a form of LGA (38x38x2mm)
or as a module with high-density connectors.

Sponsored by:	Device Solutions
2014-02-24 19:32:15 +00:00
ian
a0e8831378 Add the bits needed to run SMP on imx6.
The 'option SMP' isn't added to the kernel config yet; people wanting to
test this have to opt-in for now.
2014-02-24 03:51:31 +00:00
ian
6dd8bc5032 Invalidate caches immediately upon entry to init_secondary(). Also set
the Bufferable bit in the PDE entries of the secondary processor startup
pagetables.

The caches really need to be invalidated even earlier than this, but this
is a big step in the right direction.  The invalidate needs to happen
before the MMU is enabled, which means it has to be called from asm code
that's running with physical addressing.  Fixing that will be handled in
a future change.
2014-02-24 03:47:39 +00:00
ian
a260b08139 Add a new cache maintenance function, idcache_inv_all, to the table, and
implementations for each of the chips we support.  Most chips up through
armv6 can use the armv4 implementation which has a single coprocessor
opcode for this operation.  The rather more complex armv7 implementation
comes from netbsd.
2014-02-24 01:41:58 +00:00
ian
9f6aae0da4 Add an ident line. 2014-02-24 01:17:23 +00:00
ian
cbe10f27ad Actually set the proper bit to indicate TTB shared memory.
Submitted by:	Juergan Weiss
2014-02-23 23:06:50 +00:00
ian
d45f81d37a If the L2 cache type is PIPT, pass a physical address for a flush.
While this is technically more correct, I don't think it much matters,
because the only thing in the tree that calls cpu_flush_dcache() is md(4)
and I'm > 99% sure it's bogus that it does so; md has no ability to do
anything that can perturb data cache coherency.
2014-02-23 22:52:48 +00:00
ian
bce9295acb Move the declaration for mpentry() into a header file instead of pasting
it into a bunch of different .c files.  Remove declarations for the unused
mptramp() function from everywhere except AramadaXP (and I think it's
really not used there either, because the code that references it appears
to be insanely does-nothing in nature).
2014-02-23 22:35:18 +00:00
ian
5931a18696 Eliminate an unused-var warning by wrapping #if 0 around some tables of
values that were probably entered "for completeness" from a datasheet, and
for all I know may be useful/necessary some day.
2014-02-23 22:29:59 +00:00
ian
3b515730da Fix a typo _IMX51_TZICRREG_H_ -> _IMX51_TZICREG_H_ (extra R) 2014-02-23 21:13:04 +00:00
ian
3c9c635c3b Don't force bootverbose on anymore, it can be set from ubldr now. 2014-02-23 01:49:01 +00:00
ian
cf272e7d33 Create a generic IMX6 kernel config. This is based on the existing
WANDBOARD.common config, but with the freescale-specific optons and devices
all together at the bottom now.  In addition to reformatting and shuffling
lines around, two new options are added because they're now known to work,
VFP and FREEBSD_BOOT_LOADER.

This config does not include any static DTB, it requires that u-boot
provide a DTB (or a custom kernel config can compile one in).

This will supercede all the existing WANDBOARD* configs, but those will
be left around for a while to help people transition their customized
configs to include this new one instead.
2014-02-23 01:48:07 +00:00
ian
b978d5975b Add the FREEBSD_BOOT_LOADER option so that a loaded DTB passed in from
ubldr will actually get used.
2014-02-23 01:37:29 +00:00
ian
93f036b416 Add basic cpu frequency control and temperature monitoring to imx6_anatop.
The temperature monitor device is enabled to sample the die temperature at
16hz.  The temperature is published via sysctl.  A callout routine at 10hz
monitors the temperature and throttles back the cpu if the temperature
goes over a user-settable throttle point (by default 10C less than the
critical high-point temperature for the chip).  The hardware is supposed
to be able to deliver an interrupt when the temperature exceeds a settable
limit, but the interrupt never arrives so for now a callout does the job.

At attach time we read the maximum cpu frequency the chip is allowed to run
at and the cpu is set to run at that speed.  It's reported at attach time.
A sysctl variable reports the current speed when queried.

New sysctl values:

  dev.imx6_anatop.0.cpu_mhz: 984
  dev.imx6_anatop.0.temperature: 37.9C
  dev.imx6_anatop.0.throttle_temperature: 95.0C

Steven Lawrance did the initial heavy lifting on this, but I changed
enough stuff that I'm the one to blame if anything breaks.

Submitted by:	Steven Lawrance <stl@koffein.net>
2014-02-21 06:00:06 +00:00
imp
b5a71d5e66 Remove bogus blank line. 2014-02-21 05:17:30 +00:00
ian
7de199d4c4 Add early printf support, wrapped in #if 0 because it's only rarely needed. 2014-02-20 14:29:59 +00:00
ian
6bd122754e Give the fdt helper routines static linkage since no global definition
of them is provided anywhere.  (gcc was nice enough to warn about this,
clang didn't for some reason.)
2014-02-17 20:04:57 +00:00
jhay
3b760d926d Make it possible to use the env kernel config file option for AVILA
and CAMBRIA boards that does not use loader to load the kernel. This
is basically how it was done for i386. This way tunables can also be
set. For example in config file:

env "/conf/AVILA.env"

And in AVILA.env:

vfs.unmapped_buf_allowed=0

MFC after:	2 weeks
2014-02-17 11:05:57 +00:00
br
dbb2be7f15 - Decrease buffer size.
- Handle eDMA interrupt on running channel only.
2014-02-16 19:21:44 +00:00
br
0c8f485c94 Add driver for Synchronous Audio Interface (SAI).
SAI supports full-duplex serial interfaces with frame
synchronization such as I2S, AC97, TDM, and codec/DSP
interfaces.
2014-02-16 16:49:54 +00:00
ian
1431a5d9b9 Oops, remove some dregs of debugging. 2014-02-16 03:30:22 +00:00
ian
bfc46c3238 Make it possible to access the ocotp registers before the ocotp device
is attached, by establishing a temporary mapping of the registers when
necessary.  This is a temporary measure to keep progress moving; in the
long run we need better control over the order in which devices attach
(better than "the order they appear in the fdt dts source").
2014-02-16 03:09:39 +00:00
ian
aa7c8cae90 Sweep up a couple crumbs left over from the imx6->fsl renaming. 2014-02-15 21:59:00 +00:00
ian
2be94cb523 It turns out Freescale cleverly made the ocotp device compatible across
several different families of SoCs, so move it to the freescale directory
and prefix everything with fsl rather than imx6.
2014-02-15 21:21:57 +00:00
ian
882689c353 Convert the "R1B fix" from a busy-loop in the interrupt handler to a callout. 2014-02-15 17:55:35 +00:00
ian
2cb62fce97 Add a driver to provide access to imx6 on-chip one-time-programmble data.
Submitted by:	Steven Lawrance <stl@koffein.net>
2014-02-15 17:19:55 +00:00
zbb
54cfadd9cd Handle pmap_enter() on already promoted mappings for ARMv6/v7
Attempt to demote the superpage if trying to pmap_enter() on
one. Panic only when the particular superpage should
no longer exist for that pmap and address.
2014-02-15 13:27:45 +00:00
zbb
3b9ba9750b Remove spurious assertion from pmap_extract_locked() on ARM
The condition under assertion is no longer valid since
superpages support is operating on section mappings.
2014-02-15 13:24:58 +00:00
zbb
6164a744fe Avoid redundant superpage promotion attempts on ARM
Because pmap_enter_locked() is called from few different functions
some redundancy in superpage promotion attempts can be observed.
Hence, avoid promotion in pmap_enter_object() (if the object can
be mapped by superpage it will be handled by pmap_enter_object()
itself) and also do not waste time in pmap_enter_quick().
From now on the promotion will be performed only in pmap_enter().
2014-02-15 13:22:37 +00:00
zbb
e89c3bab1f Fix superpage promotion on ARM with respect to RO/RW and wired attributes
It was possible to create RW superpage mapping even if
the base pages were RO due to wrong setting of the prot
flag passed to pmap_map_section().
Promotion attempt should be canceled in case of attributes
mismatch between any two base pages. Since we still use
pv_flags to maintain permission to write (PVF_WRITE) and
wired status (PVF_WIRED) for a page, it is also necessary
to take those variables into account.
2014-02-15 13:20:17 +00:00
zbb
f3152cdd31 Ensure proper TLB invalidation on superpage promotion and demotion on ARM
Base pages within newly created superpage need to be invalidated so that
new mapping is "visible" immediately after creation.
2014-02-15 13:17:51 +00:00
zbb
2edbe39b71 Always clear L1 PTE descriptor when removing superpage on ARM
Invalidate L1 PTE regardles of existance of the corresponding
l2_bucket. This is relevant when superpage is entered via
pmap_enter_object() and will fix crash on entering page
in place of not properly removed superpage.
2014-02-15 13:13:00 +00:00
brueffer
1693f71657 Correct the order of arguments to mtx_init().
PR:		186701
Submitted by:	Takanori Sawada <tak.swd at gmail.com>
MFC after:	2 weeks
2014-02-14 11:18:15 +00:00
andrew
dbe8cc71f1 Allow the kernel to be loaded at any 1MiB address. This requirement is
because we use the 1MiB section maps as they only need a single pagetable.

To allow this we only use pc relative loads to ensure we only load from
physical addresses until we are running from a known virtual address.

As a side effect any data from before or 64MiB after the kernel needs to
be mapped in to be used. This should not be an issue for kernels loaded
with ubldr as it places this data just after the kernel. It will be a
problem when loading directly from anything using the Linux ABI that
places the ATAG data outside this range, for example U-Boot.
2014-02-13 21:30:54 +00:00
ian
2b9e255000 Remove a couple obsolete function declarations. 2014-02-13 19:14:23 +00:00
loos
ab3f62ff43 Make the gpioled(4) work out of the box on BBB.
Add gpioled(4) to BEAGLEBONE kernel and add the description of the four
on-board leds of beaglebone-black to its DTS file.

Approved by:	adrian (mentor, implicit)
2014-02-13 18:51:37 +00:00
loos
375cec5973 Allow the use of the OFW GPIO bus for ti_gpio and bcm2835_gpio. With this
change the gpio children can be described as directly connected to the GPIO
controller without the need of describing the OFW GPIO bus itself on the
DTS file.

With this commit the OFW GPIO bus is fully functional on BBB and RPi.

GPIO controllers which want to use the OFW GPIO bus will need similar
changes.

Approved by:	adrian (mentor, implicit)
2014-02-13 18:42:23 +00:00
imp
bc45fe580c Honor the disabled status by only grabbing resources and returning
when running under FDT.
2014-02-13 16:50:08 +00:00
imp
9ecad450cb Fix board ID too... 2014-02-13 15:47:41 +00:00
imp
875b628e17 Fix board name. 2014-02-13 15:46:08 +00:00
br
803f6663ca Add function for configuring PLL4 (Audio) clock frequency output. 2014-02-13 06:38:01 +00:00
ian
86ac81dac6 Add handling of standard "non-removable" property, and also some workaround
code so that if card detect is wired to a gpio pin, for now we just treat
it the same as non-removable (because there isn't a gpio driver yet).
2014-02-13 03:45:33 +00:00
ian
d9b84ac407 Write translation code for the SDHCI_PRESENT_STATE register. Freescale
moved some bits around in their version of the register, adjust things
so that the sdhci code sees the standard layout.
2014-02-13 02:38:16 +00:00
ian
03444312d7 Use the same logic as the x86 platforms to avoid trying perform fault fixup
while in a critical section or while holding a non-sleepable lock.

Reviewed by:	cognet
2014-02-12 20:09:27 +00:00
ian
64c07b454d Use the right symbols for determining arm architecture. Include the
necessary header file which has the new FAULT_WNR symbol defined in it.
2014-02-12 19:59:30 +00:00
ian
722eaf0a07 On armv6 and later, use the WriteNotRead bit of the fault status register
to decide what protections are required by the faulting access.  The old
code disassembled the faulting instruction, and there are a lot of new
instructions that aren't handled.  The old code is still used for armv4/5
which doesn't have the WNR bit)
2014-02-12 18:55:26 +00:00