Commit Graph

7 Commits

Author SHA1 Message Date
Adrian Chadd
cc641d93c6 Fix GPIO_MAXPINS calculation for the AR71xx, AR724x, AR913x SoC.
Submitted by:	Luiz Otavio O Souza <loos.br@gmail.com>
2011-05-06 02:45:02 +00:00
Adrian Chadd
d7fc7abf5a Add some initial PCIe bridge support for the AR724x chipsets.
This is reported to work on the AR7240 based Ubiquiti Rocket M5
but I haven't tested it on that hardware. I also don't yet have
it fully working on the AR7242 based development board here;
probe/attach functions but the register space resource looks like
the endian-ness is wrong (0x10000000 instead of 0x00001000).o

Further digging will be required.

Submitted by:	Luiz Otavio O Souza
2011-04-30 11:36:16 +00:00
Adrian Chadd
c746f80ee3 Add the IP2 DDR flush handlers.
These aren't yet used in the interrupt handler path but should be.
2011-04-28 11:13:26 +00:00
Adrian Chadd
eab9f72a5a Implement AR724x USB initialisation code.
This (again) still requires an offset for the AR913x/AR724x before USB will
function.

Submitted by: Luiz Otavio O Souzau <loos.br@gmail.com>
2011-03-31 02:36:22 +00:00
Adrian Chadd
c55baa23d8 Add the missing AR724x DDR flush routines for if_arge0.
Submitted by: Luiz Otavio O Souza
2011-03-13 08:36:57 +00:00
Adrian Chadd
c4df93502d Add some initial AR724X chipset support.
This is untested but should at least allow an AR724X to boot.

The current code is lacking the detail needed to expose the PCIe bus.
It is also lacking any NIC, PLL or flush/WB code.
2010-08-19 11:53:55 +00:00
Adrian Chadd
7f8184068f Import initial AR91XX and AR724X CPU register definitions.
Obtained from:	Linux
2010-08-18 00:26:14 +00:00