PL (programmable logic) uses FCLK0..FCLK3 as a clock sources.
Normally they're configured by first stage boot loader (FSBL)
and normal user never has to touch them. These sysctls may come
useful for hardware developers
hw.fpga.fclk.N.source: clock source (IO, DDR, ARM)
hw.fpga.fclk.N.freq: requested frequency in Hz
hw.fpga.fclk.N.actual_freq: actual frequency in Hz (R/O)
hw.fgpa.level_shifters: 0/1 to enable/disable PS-PL level shifters,
normally they're enabled either by FSBL or after programming
FPGA through devcfg(4)
that it can connect to switches at speeds other than 1gb.
This requires changing the reference clock speed. Since we still don't
have a general clock API that lets a SoC-independant driver manipulate its
own clocks, this change includes a weak reference to a routine named
cgem_set_ref_clk(). The default implementation is a no-op; SoC-specific
code can provide an implementation that actually changes the speed.
Submitted by: Thomas Skibo <ThomasSkibo@sbcglobal.net>
Communication on src-commiters, Sat, 27 Apr 2013 22:09:06 -0700,
Subject was: "Re: svn commit: r249997"
As I'm here, fix the style main block comments in files' headers.
