Disable "cache line streaming" for aic7890/91 Rev A chips. I
have never seen these chips fail using this feature, but
some of Adaptec's regression tests have.
Explicitly set "cache line streaming" to on for aic7896/97
chips. This was happening before, but this documents the
fact that these chips will not function correctly without
CACHETHEEN set.
aic7xxx.h:
Add new bug types.
Fix a typo in a comment.
aic7xxx.reg:
Add a definition for the SHVALID bit in SSTAT3 for Ultra2/3
chips. This bit inicates whether the bottom most (current)
element in the S/G fifo has exhausted its data count.
aic7xxx.seq:
Be more careful in how we turn off the secondary DMA channel.
Being less careful may hang the PCI bus arbitor that negotiates
between the two DMA engines.
Remove an unecessary and incorrect flag set operation in
the overrun case.
On Ultra2/3 controllers, clear the dma FIFO before starting
to handle an overrun. We don't want any residual bytes from
the beginning of the overrun to cause the code that shuts
down the DMA engine from hanging because the FIFO is not
(and never will be) empty.
If the data fifo is empty by the time we notice that a
read transaction has completed, there is no need to
hit the flush bit on aic7890/91 hardware that will not
perform an auto-flush. Skip some cycles by short circuiting
the manual flush code in this case.
When transitioning out of data phase, make sure that we
have the next S/G element loaded for the following
reconnect if there is more work to do. The code
would do this in most cases before, but there was
a small window where the current S/G element could
be exhausted before our fetch of the next S/G element
completed. Since the S/G fetch is already initiated
at this point, it makes sense to just wait for the
segment to arrive instead of incuring even more latency
by canceling the fetch and initiating it later.
Fast path the end of data phase handling for the last
S/G segment. In the general case, we might have
worked ahead a bit by stuffing the S/G FIFO with
additional segments. If we stop before using them
all, we need to fixup our location in the S/G stream.
Since we can't work past the last S/G segment, no
fixups are ever required if we stop somewhere in
that final segment.
Fix a little buglet in the target mode dma bug handler.
We were employing the workaround in all cases instead
of only for the chips that require it.
Fix the cause of SCB timeouts and possible "lost data"
during read operations on the aic7890. When sending
a data on any Ultra2/3 controller, the final segment
must be marked as such so the FIFO will be flushed and
cleaned up correctly when the transfer is ended. We
failed to do this for the CDB transfer and so, if
the target immediately transfered from command to data
phase without an intervening disconnection, the first
segment transferred would be any residual bytes from
the cdb transfer. The Ultra160 controllers for some
reason were not affected by this problem.
Many Thanks to Tor Egge for bringing the aic7890 problem
to my attention, providing analysis, as well as a mechanism
to reproduce the problem.
is not desired, then the user can register an EV_SIGNAL filter to
explicitly catch a signal event.
Change requested by: jayanth, ps, peter
"Why is kevent non-restartable after a signal?"
stored at a different location in the PCI space, so adjust accordingly.
Also, when using more than two smart controllers in one machine, the
disks were assigned the wrong drive number; fix this as well.
Add hints towards login.conf(5), which should be the preferred way
to set this systemwide without having to worry about the shell used.
PR: 9245
Submitted by: martin Kammerhofer <dada@sbox.tu-graz.ac.at>
This is in fact an Intel Orion chipset (82454KX/GX) which has been used
in HP NetServer's LS4 range.
HP Probably relabeled the DID. That's the only explanation I can find
plausible to this `mystery'.
doesn't exist. This could bite you by allowing you merrily install your
modules one on top of the other as the regular file ${DESTDIR}/modules
and think it completed properly...
operation or after it. If the ktrace operation was enabled while the
process was blocked doing IO, the race would allow it to pass down
invalid (uninitialized) data and panic later down the call stack.
the 12.4.11 firmware with a few changes to the link handling code merged
in from the 12.4.13 release. I'm doing this because the 12.4.13 firmware
doesn't seem to handle 10/100 link settings properly on 1000baseT cards.
Note that the revision codes still identify the firmware as 12.4.13
because both ti_fw2.h and ti_fw.h have to have the same revision values,
and I wanted to keep the 12.4.13 firmware for Tigon 1 cards.
It's nice to have firmware source.
certain uses of snapshots and currently appears to be causing some
other problems. So for now, I am reverting to the old semantics until
I have had time to investigate what is causing the other problems.
the SF_IMMUTABLE flag to prevent writing. Instead put in explicit
checking for the SF_SNAPSHOT flag in the appropriate places. With
this change, it is now possible to rename and link to snapshot files.
It is also possible to set or clear any of the owner, group, or
other read bits on the file, though none of the write or execute
bits can be set. There is also an explicit test to prevent the
setting or clearing of the SF_SNAPSHOT flag via chflags() or
fchflags(). Note also that the modify time cannot be changed as
it needs to accurately reflect the time that the snapshot was taken.
Submitted by: Robert Watson <rwatson@FreeBSD.org>
allow for that.
o Remember to call NDFREE() if exiting as a result of a failed
vn_start_write() when snapshotting.
Reviewed by: mckusick
Obtained from: TrustedBSD Project
The regulations has been changed to adopt 802.11b since Oct. 99.
For 11Mbps NICs sold in Japan, all DS channels (1..14) are available.
Thank you, itojun.
Obtained from: NetBSD:basesrc/usr.sbin/wiconfig/wiconfig.8 Rev.1.5 ->1.6
and emit a warning. This is a security measure since ldconfig
influences the shared libraries used by all programs.
I think the check should be made even more stringent by also
ignoring group-writable directories. I will make that change soon
unless we encounter a good reason not to do it.
Submitted by: Maxime Henrion <mhenrion@cybercable.fr>
Formerly the init functions were called in the opposite of the
order in which libraries were loaded, and libraries were loaded
according to a breadth-first traversal of the dependency graph.
That ordering came from SVR4.0, and it was easy to implement but
not always sensible.
Now we do a depth-first walk over the dependency graph and call
the init functions in an order such that each shared object's needed
objects are initialized before the shared object itself. At the
same time we build a list of finalization (fini) functions in the
opposite order, to guarantee correct C++ destructor ordering whenever
possible. (It may not be possible if dlopen and dlclose are used
in strange ways, but we come as close as one can come.)
The need for this renovation has become apparent as more programs
have started using multithreading. The multithreaded C library
libc_r requires initialization, whereas the standard libc does not.
Since virtually every other object depends on the C library, it is
important that it get initialized first.
3.3.6 base distribution, some of the packing lists needed hacking so that
they would pack up everything in the right place. As a result, go ahead and
just add a directory for the packing lists. These are the i386 packing lists.
corresponding tarball from it. It uses the packing list name to determine
the tarball name. If the tarball name ends in 'gz', it will be gzipped, if
it ends in 'bz', it will be bzip2'd.
XFree86 3.3.6 into a scratch directory. The patch file patches the XFree86
port to not ask any questions and to actually be able to install some things
like the i810 server link kit bits. If you want XF86Setup to build, you
should have tk80 (not tk82) installed. If you want to XF86Setup_jp to build
you need to have ja-tk80 installed.
