2065 Commits

Author SHA1 Message Date
adrian
b5a61383ac Add a MII mode for SGMII.
This appears on the AR934x and later chips, although it's not
something that's programmed via the arge0/arge1 register space.
It's just cosmetic.
2015-03-02 01:23:59 +00:00
adrian
a065c9d2dc Add very initial QCA955x awareness to the GPIO code.
There's a lot more to come - the QCA955x has a bunch more GPIO MUX
configuration, reminiscent of what the ARM chips let you do - but
it'll have to come later.
2015-03-01 07:00:34 +00:00
adrian
90aba284a2 Flesh out some more QCA955x ethernet PLL setup. 2015-03-01 06:59:32 +00:00
adrian
3664d4bf70 Add Ethernet PLL values for the QCA955x.
These are the same as the AR934x.

Obtained from:	Linux openwrt
2015-03-01 06:54:59 +00:00
adrian
0525b8f3b9 Make QCA955X_GMAC_REG_ETH_CFG defined like most other registers like this. 2015-03-01 06:52:23 +00:00
adrian
9709e28ab3 Add QCA955x support to the EHCI setup path.
Tested:

* QCA AP135 development board, USB rootfs.
2015-03-01 06:05:01 +00:00
jchandra
3bce428c24 Whitespace fixes for sys/mips/nlm/dev
Clean up whitespace issues under sys/mips/nlm/dev. No functional
change in this commit.
2015-02-28 00:22:10 +00:00
jchandra
707f63ee61 Whitespace fixes for files in sys/mips/nlm
Clean up whitespace issues under sys/mips/nlm (except dev). No
functional change in this commit.
2015-02-28 00:17:29 +00:00
jchandra
b0eaf97404 Add subclass of simplebus for Broadcom XLP
This will override the resource allocation of simplebus, and also
merge the resource allocation code which was in xlp_pci.c.

With this change the SoC devices that does not have proper PCI
resources will be on the FDT simplebus. We can remove
sys/mips/nlm/dev/cfi_pci_xlp.c and sys/mips/nlm/dev/uart_pci_xlp.c
2015-02-27 23:33:53 +00:00
jchandra
ba32078fbc Move PCI bus below simplebus for Broadcom XLP
This will enable us to do common allocation code for memory and
interrupts for SoC devices as well as PCI devices.
2015-02-27 02:21:52 +00:00
jchandra
1f4069c7a5 Improve additional interrupt ACK for Broadcom XLP
Handling some interrupts in XLP (like PCIe and SATA) involves writing to
vendor specific registers as part of interrupt acknowledgement.

This was earlier done with xlp_establish_intr(), but a better solution
is to provide a function xlp_set_bus_ack() that can be used with
cpu_establish_hardintr(). This will allow platform initialization code to
setup these ACKs without changing the standrard drivers.
2015-02-27 00:57:09 +00:00
jchandra
4d42a57ca7 Remove run-time allocation of XLP IRQs
Follow the same static IRQ to Interrupt Table Entry mapping as the other
OS supported on XLP.
2015-02-26 02:22:47 +00:00
jchandra
00251f90bc Add netlogic,xlp-pic as interrupt controller for XLP
Add an empty driver for netlogic,xlp-pic to ensure that the device tree
is correct and has an interrupt controller.
2015-02-26 02:05:45 +00:00
jchandra
05a9f93ae4 Fix up interrupt definitions for Broadcom XLP
Gather all the IRQ definitions to interrupt.h. Earlier these were in xlp.h
and pic.h.  Update the definition of XLP_IRQ_IS_PICINTR to check for last
irq as well.
2015-02-26 01:53:24 +00:00
adrian
bf6c1ce2ba Remove this - I made it all work again a looong time ago. 2015-02-16 02:05:34 +00:00
sbruno
fce5f51901 The linux driver code for the MDIO bus does a read-after-write
which seems to be required on MIPS74k platforms for correct
behaviour.

Reviewed by:	adrian
2015-02-02 17:33:00 +00:00
kib
3bbc91d138 Do not qualify the mcontext_t *mcp argument for set_mcontext(9) as
const.  On x86, even after the machine context is supposedly read into
the struct ucontext, lazy FPU state save code might only mark the FPU
data as hardware-owned.  Later, set_fpcontext() needs to fetch the
state from hardware, modifying the *mcp.

The set_mcontext(9) is called from sigreturn(2) and setcontext(2)
implementations and old create_thread(2) interface, which throw the
*mcp out after the set_mcontext() call.

Reported by:	dim
Discussed with:	jhb
Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
2015-01-31 21:43:46 +00:00
loos
5e1a593992 Implement GPIO_GET_BUS() method for all GPIO drivers.
Add helper routines to deal with attach and detach of gpiobus and gpioc
devices that are common to all drivers.
2015-01-31 19:32:14 +00:00
loos
b76f0f0c1f Replace spaces with tabs, this will easier future changes on softc
structure.

No functional changes.
2015-01-31 12:43:30 +00:00
loos
a2924f5fee Clean up and fix the device detach routine and the failure path on GPIO
drivers.

This paves the way for upcoming work.
2015-01-31 12:17:07 +00:00
kib
b8f7b5ec8d Remove Giant from /dev/mem and /dev/kmem. It is definitely not needed
for i386, and from the code inspection, nothing in the
arm/mips/sparc64 implementations depends on it.

Discussed with:	imp, nwhitehorn
Sponsored by:	The FreeBSD Foundation
MFC after:	3 weeks
2015-01-24 12:51:15 +00:00
br
5a896dc0ff Add 128-byte cache flushing routines.
Leave CNMIPS untouched as these functions depends on config2
register.
2015-01-20 11:10:25 +00:00
bz
d20f0a2401 Move MALTA_COMMON to std.MALTA (as we have for XLP and SWARM).
This avoids universe trying to build MALTA_COMMON and fail due to
the problem addressed in r276773.
Include std.MALTA from the MALTA mipsel and MALTA64 mips64el config files,
where the machine lines exist.
2015-01-07 12:12:36 +00:00
bz
2fbe376a24 Remove the machine directive from the common MALTA* configuration file
to avoid conflicting machine lines for the MALTA64 kernel configuration
making config(8) go barf and builds to fail.

Pointed out by:	adrian
2015-01-07 01:41:45 +00:00
markj
7e7e145818 Factor out duplicated code from dumpsys() on each architecture into generic
code in sys/kern/kern_dump.c. Most dumpsys() implementations are nearly
identical and simply redefine a number of constants and helper subroutines;
a generic implementation will make it easier to implement features around
kernel core dumps. This change does not alter any minidump code and should
have no functional impact.

PR:		193873
Differential Revision:	https://reviews.freebsd.org/D904
Submitted by:	Conrad Meyer <conrad.meyer@isilon.com>
Reviewed by:	jhibbits (earlier version)
Sponsored by:	EMC / Isilon Storage Division
2015-01-07 01:01:39 +00:00
jhb
c3d1954342 Remove "New" label from NFSCL/NFSD now that they are the only NFS
client/server.  While here, remove duplicate NFSCL from sys/conf/NOTES.

Approved by:	rmacklem
2015-01-06 16:15:57 +00:00
rwatson
60909669f0 In order to reduce use of M_EXT outside of the mbuf allocator and
socket-buffer implementations, introduce a return value for MCLGET()
(and m_cljget() that underlies it) to allow the caller to avoid testing
M_EXT itself.  Update all callers to use the return value.

With this change, very few network device drivers remain aware of
M_EXT; the primary exceptions lie in mbuf-chain pretty printers for
debugging, and in a few cases, custom mbuf and cluster allocation
implementations.

NB: This is a difficult-to-test change as it touches many drivers for
which I don't have physical devices.  Instead we've gone for intensive
review, but further post-commit review would definitely be appreciated
to spot errors where changes could not easily be made mechanically,
but were largely mechanical in nature.

Differential Revision:	https://reviews.freebsd.org/D1440
Reviewed by:	adrian, bz, gnn
Sponsored by:	EMC / Isilon Storage Division
2015-01-06 12:59:37 +00:00
adrian
be883ba4fe Make the apb.c code optional behind ar71xx_apb rather than standard.
The QCA955x has more mux interrupts going on - and the AR934x actually does,
but I cheated and assigned wlan and pcie to the same interrupt line.
They are, there's just a status register mux that I should've been using.

Luckily this isn't too bad a change in itself - almost all of the
Atheros MIPS configurations use a _BASE file to inherit from.
Except PB92, which I should really fix up at some point.

The AR934x will use the legacy apb for now until I write its replacement.

The QCA955x SoC I'm doing bring-up on will have a separate qca955x_apb.c
implementation that includes hooking into IP2/IP3 and doing further
interrupt demuxing as appropriate.
2015-01-06 07:43:07 +00:00
adrian
e8134b8e7d Add an APB base/size for the QCA955X for an upcoming QCA955x specific
APB mux.

It's larger than the AR71xx because it needs to replace the nexus
for some devices (notably wifi) and the wifi driver (if_ath_ahb.c)
reads the SPI data directly at early boot whilst it's memory mapped
in.

I'm eventually going to rip it out and replace it with a firmware
interface similar to what exists for the if_ath_pci.c path -
something early on (likely something new that I'll write) will
suck in the calibration data into a firmware API blob and that'll
be accessed from if_ath_ahb.c.

But, one thing at a time.

Tested:

* QCA955x SoC, AP135 development board
2015-01-06 07:37:33 +00:00
adrian
eeb397aba0 The QCA955x USB init path doesn't require any of this, so delete it.
Obtained from:	Linux/OpenWRT
2015-01-06 07:35:05 +00:00
rodrigc
eeb56aacdf Add some GEOM options. 2015-01-06 05:28:22 +00:00
rodrigc
de4fd944bb Refactor common options from MALTA and MALTA64 kernel
configs into MALTA_COMMON file.
2015-01-06 05:26:13 +00:00
hselasky
63ec340209 Add 64-bit DMA support in the XHCI controller driver.
- Fix some comments and whitespace while at it.

MFC after:	1 month
Submitted by:	marius@
2015-01-05 20:22:18 +00:00
adrian
72a716f320 Remove the remnants of the OpenWRT/Linux bits that this was based off
of.

Obtained from:	Linux/OpenWRT
2015-01-05 05:30:07 +00:00
adrian
ad79abc364 Oops - missed refclk.
Tested:

* AP135, QCA955x SoC
2015-01-05 05:26:57 +00:00
adrian
d119230495 Add initial Qualcomm Atheros QCA955x SoC support.
This adds the initial frequency poking and configures up enough
for it to boot and spit out data over the console.

There's still a whole bunch of work to do in the reset path
and devices to support this thing, but hey, it's alive!

ath> go 0x80050100
## Starting application at 0x80050100 ...
CPU platform: Atheros AR9558 rev 0
CPU Frequency=720 MHz
CPU DDR Frequency=600 MHz
CPU AHB Frequency=200 MHz
platform frequency: 720 MHz
CPU reference clock: 0 MHz
CPU MDIO clock: 40 MHz

Done at:	hackathon
Obtained from:	Linux OpenWRT, Qualcomm Atheros
2015-01-05 02:06:26 +00:00
adrian
fca8e06eab ACK interrupts on the new SoCs. 2015-01-05 02:00:41 +00:00
adrian
d2d1da27e3 add QCA955x SoC types. 2015-01-05 01:59:44 +00:00
adrian
8a2fc581eb Add QCA955x series register definitions.
There's likely a bunch of register offsets that I have to add the
register window base to before I use them.

Done at:	Hackathon
Obtained from:	Linux OpenWRT
2015-01-05 01:44:23 +00:00
adrian
92005e6093 Add a GPIO output mux configuration method.
The AR934x and later (which will turn up eventually) have a new GPIO
output configuration option - a real MUX rather than a "GPIO or this
function."

For now I'm squirreling it away in the CPU code just so it's done -
I may move this to the GPIO layer later.

Specifically, this is required for setting up some boards that have
external receive side LNA (low noise amplifier) that gets switched on/off
by the on-chip wireless MAC.  If we don't add this support for those
boards then we'll end up with really poor performance.

(I don't yet have one of those APs, but it'll likely show up in a week.)

Obtained from:	Linux OpenWRT
2015-01-03 06:55:58 +00:00
adrian
a505f86799 Add AR934x specific GPIO functions and output MUX configuration.
Obtained from:	Linux OpenWRT
2015-01-03 06:35:53 +00:00
adrian
1bc6b102d6 Add AR934x GPIO function configuration.
Obtained from:	Linux OpenWRT
2015-01-03 06:30:30 +00:00
adrian
3662c835fe For now build random into the kernel - there seems to be issues kldload'ing
it at early boot.
2015-01-03 02:39:28 +00:00
adrian
8ddd21d3e3 The kernel has gotten too big; trim out MSDOSFS for the DIR825B1. 2015-01-03 02:34:23 +00:00
emaste
5506fd85be Update ELF headers to include additional defines
The elftoolchain project includes these additional defines for various
userland programs. Given that arch-specific defines are still interesting
in the context of userland programs reading or writing ELF metadata, they
should be included in top-level ELF headers.

Remove duplicate defines from ARM and MIPS elf headers.

Submitted by:	will (initial version)
Reviewed by:	imp, will
Sponsored by:	The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D844
2015-01-02 15:36:29 +00:00
alc
369e66acd7 The physical memory allocator supports the use of distinct free lists for
managing pages from different address ranges.  Generally speaking, this
feature is used to increase the likelihood that physical pages are
available that can meet special DMA requirements or can be accessed through
a limited-coverage direct mapping (e.g., MIPS).  However, prior to this
change, the configuration of the free lists was static, i.e., it was
determined at compile time.  Consequentally, free lists could be created
for address ranges that held no actual pages, for example, on 32-bit MIPS-
based systems with 512 MB or less of physical memory.  This change makes
the creation of the free lists dynamic, i.e., it is based on the available
physical memory at boot time.

On 64-bit x86-based systems with 64 GB or more of physical memory, create
free lists for managing pages with physical addresses below 4 GB.  This
change is to address reported problems with initializing devices that
require the allocation of physical pages below 4 GB on some systems with
128 GB or more of physical memory.

PR:		185727
Differential Revision:	https://reviews.freebsd.org/D1274
Reviewed by:	jhb, kib
MFC after:	3 weeks
Sponsored by:	EMC / Isilon Storage Division
2014-12-31 00:54:38 +00:00
markj
7ea63e4fb4 Restore the trap type argument to the DTrace trap hook, removed in r268600.
It's redundant at the moment since it can be obtained from the trapframe
on the architectures where DTrace is supported, but this won't be the case
with ARM.
2014-12-23 15:38:19 +00:00
br
936d6a03d2 Correct the end address of the memory regions.
Pointed out by:	ian
2014-12-19 12:09:29 +00:00
br
2df3680ba6 Add configuration files for BERI soft-core synthesized on
Terasic SoCKit board (Altera FPGA).

Use virtio block as root filesystem device.

Sponsored by:	DARPA, AFRL
2014-12-17 11:36:31 +00:00
br
ed522fedd4 Use memory regions information provided in FDT.
Reviewed by:	brooks
Sponsored by:	DARPA, AFRL
2014-12-17 09:34:54 +00:00