80639 Commits

Author SHA1 Message Date
bz
abd6b4ebb7 Add ddb support to the "new" link layer code ("new-arp"):
- show all lltables [1] (optional flag to also show the llentries as well)
 - show lltable <struct lltable *>
 - show llentry <struct llentry *>

MFC after:	6 days
2010-03-18 09:09:59 +00:00
ed
fbf3d99d10 Remove an unneeded variable.
Reported by:	tinderbox
2010-03-18 07:35:20 +00:00
imp
b55593dee5 Remove two instances of the evil hack to get the ifnet. mii_ifp is
set early enough that we don't need to do these hacks anymore.
2010-03-17 22:45:53 +00:00
marius
0c9a31ed99 o Add support for UltraSparc-IV+:
- Swap the configuration of the first and second large dTLB as with
    US-IV+ these can only hold entries of certain page sizes each, which
    we happened to chose the non-working way around.
  - Additionally ensure that the large iTLB is set up to hold 8k pages
    (currently this happens to be a NOP though).
  - Add a workaround for US-IV+ erratum #2.
  - Turn off dTLB parity error reporting as otherwise we get seemingly
    false positives when copying in the user window by simulating a
    fill trap on return to usermode. Given that these parity errors can
    be avoided by disabling multi issue mode and the problem could be
    reproduced with a second machine this appears to be a silicon bug of
    some sort.
  - Add a membar #Sync also before the stores to ASI_DCACHE_TAG. While
    at it, turn of interrupts across the whole cheetah_cache_flush() for
    simplicity instead of around every flush. This should have next to no
    impact as for cheetah-class machines we typically only need to flush
    the caches a few times during boot when recovering from peeking/poking
    non-existent PCI devices, if at all.
  - Just use KERNBASE for FLUSH as we also do elsewhere as the US-IV+
    documentation doesn't seem to mention that these CPUs also ignore the
    address like previous cheetah-class CPUs do. Again the code changing
    LSU_IC is executed seldom enough that the negligible optimization of
    using %g0 instead should have no real impact.

  With these changes FreeBSD runs stable on V890 equipped with US-IV+
  and -j128 buildworlds in a loop for days are no problem. Unfortunately,
  the performance isn't were it should be as a buildworld on a 4x1.5GHz
  US-IV+ V890 takes nearly 3h while on a V440 with (theoretically) less
  powerfull 4x1.5GHz US-IIIi it takes just over 1h. It's unclear whether
  this is related to the supposed silicon bug mentioned above or due to
  another issue. The documentation (which contains a sever bug in the
  description of the bits added to the context registers though) at least
  doesn't mention any requirements for changes in the CPU handling besides
  those implemented and the cache as well as the TLB configurations and
  handling look fine.
o Re-arrange cheetah_init() so it's easier to add support for SPARC64
  V up to VIIIfx CPUs, which only require parts of this initialization.
2010-03-17 22:45:09 +00:00
qingli
8134df93ab Set the device capabilities to include dynamic link-state for
those modern drivers.

Reviewed by:	imp (and suggested by imp)
MFC after:	3 days
2010-03-17 22:12:12 +00:00
kmacy
4e6ab892f5 Cache line align various structures and move volatile counters to
not share a cache line with (mostly) immutable state

Reviewed by:	jeff@
MFC after:	7 days
2010-03-17 21:18:28 +00:00
kmacy
e10aea9e47 - cache line align arcs_lock array (h/t Marius Nuennerich)
- fix ARCS_LOCK_PAD to use architecture defined CACHE_LINE_SIZE
- cache line align buf_hash_table ht_locks array

MFC after:	7 days
2010-03-17 21:10:09 +00:00
marius
f45376263d Add macros for the VER.impl of SPARC64 II to VIIIfx. 2010-03-17 21:00:39 +00:00
marius
17a68df815 - Add TTE and context register bits for the additional page sizes supported
by UltraSparc-IV and -IV+ as well as SPARC64 V, VI, VII and VIIIfx CPUs.
- Replace TLB_PCXR_PGSZ_MASK and TLB_SCXR_PGSZ_MASK with TLB_CXR_PGSZ_MASK
  which just is the complement of TLB_CXR_CTX_MASK instead of trying to
  assemble it from the page size bits which vary across CPUs.
- Add macros for the remainder of the SFSR bits, which are useful for at
  least debugging purposes.
2010-03-17 20:23:14 +00:00
gallatin
0824be0322 Fix 2 bugs in mxge_attach()
- Don't leak slice resources when mxge_alloc_rings() fails

- Start taskq threads only after we know attach will succeed.  At
  boot time, taskqueue_terminate() will loop infinately, waiting
  for the threads to exit, and hang the system.

Submitted by: Panasas
MFC After: 3 days
2010-03-17 20:13:09 +00:00
marius
0e5db580ee - Add quirk handling for Sun Fire V1280. The firmware of these machines
provides no ino-bitmap properties so forge them using the default set
  of controller interrupts and let schizo_setup_intr() take care of the
  children, hoping for non-fancy routing.
- Add quirk handling for Sun Fire V890. When booting these machines from
  disk a Schizo comes up with PCI error residing which triggers as soon
  as we register schizo_pci_bus() even when clearing it from all involved
  registers (it's no longer indicated once we're in schizo_pci_bus()
  though). Thus make PCI bus errors non-fatal until we actually touch the
  bus. With this change schizo_pci_bus() typically triggers once during
  attach in this case. Obviously this approach isn't exactly race free
  but it's about the best we can do about this problem as we're not
  guaranteed that the interrupt will actually trigger on V890 either, as
  it certainly doesn't when for example netbooting them.
2010-03-17 20:01:01 +00:00
kmacy
bf3a24dd0d use CACHE_LINE_SIZE instead of hardcoding 128 for lock pad
pointed out by Marius Nuennerich and jhb@
2010-03-17 20:00:22 +00:00
mjacob
bc081f5e7d We actually can generate a host number.
MFC after:	1 month
2010-03-17 18:53:58 +00:00
bz
d9875d4fd4 Add pcb reference counting to the pcblist sysctl handler functions
to ensure type stability while caching the pcb pointers for the
copyout.

Reviewed by:	rwatson
MFC after:	7 days
2010-03-17 18:28:27 +00:00
mjacob
beacc60317 Put gone device timer into a structure tag that can hold more than 32 seconds. Oops.
Untangle some of the confusion about what role means when it's in the FCPARAM/SDPARAM
or isp_fc/isp_spi structures. This fixed a problem about seeing targets appear if you've
turned off autologin and find them, or rather don't, via camcontrol rescan.

MFC after:	1 month
2010-03-17 02:48:14 +00:00
marcel
a16f0fefdc Revamp the interrupt code based on the previous commit:
o   Introduce XIV, eXternal Interrupt Vector, to differentiate from
    the interrupts vectors that are offsets in the IVT (Interrupt
    Vector Table). There's a vector for external interrupts, which
    are based on the XIVs.

o   Keep track of allocated and reserved XIVs so that we can assign
    XIVs without hardcoding anything. When XIVs are allocated, an
    interrupt handler and a class is specified for the XIV. Classes
    are:
    1.  architecture-defined: XIV 15 is returned when no external
	interrupt are pending,
    2.  platform-defined: SAL reports which XIV is used to wakeup
	an AP (typically 0xFF, but it's 0x12 for the Altix 350).
    3.  inter-processor interrupts: allocated for SMP support and
	non-redirectable.
    4.  device interrupts (i.e. IRQs): allocated when devices are
	discovered and are redirectable.

o   Rewrite the central interrupt handler to call the per-XIV
    interrupt handler and rename it to ia64_handle_intr(). Move
    the per-XIV handler implementation to the file where we have
    the XIV allocation/reservation. Clock interrupt handling is
    moved to clock.c. IPI handling is moved to mp_machdep.c.

o   Drop support for the Intel 8259A because it was broken. When
    XIV 0 is received, the CPU should initiate an INTA cycle to
    obtain the interrupt vector of the 8259-based interrupt. In
    these cases the interrupt controller we should be talking to
    WRT to masking on signalling EOI is the 8259 and not the I/O
    SAPIC. This requires adriver for the Intel 8259A which isn't
    available for ia64. Thus stop pretending to support ExtINTs
    and instead panic() so that if we come across hardware that
    has an Intel 8259A, so have something real to work with.

o   With XIVs for IPIs dynamically allocatedi and also based on
    priority, define the IPI_* symbols as variables rather than
    constants. The variable holds the XIV allocated for the IPI.

o   IPI_STOP_HARD delivers a NMI if possible. Otherwise the XIV
    assigned to IPI_STOP is delivered.
2010-03-17 00:37:15 +00:00
kmacy
bd31c2114d - reduce contention by breaking up ARC state locks in to 16 for data
and 16 for metadata
- export L2ARC tunables as sysctls
- add several kstats to track L2ARC state more precisely
- avoid holding a contended lock when atomically incrementing a
  contended counter (no lock protection needed for atomics)
2010-03-16 22:17:21 +00:00
jkim
f82b4fd481 Fix a long standing regression of readdir(3) in fdescfs(5) introduced
in r1.48.  We were stopping at the first null pointer when multiple file
descriptors were opened and one in the middle was closed.  This restores
traditional behaviour of fdescfs.

MFC after:	3 days
2010-03-16 19:59:14 +00:00
qingli
4ff4954e4e Verify interface up status using its link state only
if the interface has such capability. The interface
capability flag indicates whether such capability
exists. This approach is much more backward compatible.
Physical device driver changes will be part of another
commit.

Also updated the ifconfig utility to show the LINKSTATE
capability if present.

Reviewed by:	rwatson, imp, juli
MFC after:	3 days
2010-03-16 17:59:12 +00:00
yongari
61b55f12a2 Revert r205090.
It's hard to know when the mail box register write will get flushed to
the hardware and it may take longer.

Pointed out by:	scottl
2010-03-16 17:45:16 +00:00
jhb
9654d25346 - Extend the machine check record structure to include several fields useful
for parsing model-specific and other fields in machine check events
  including the global machine check capabilities and status registers,
  CPU identification, and the FreeBSD CPU ID.
- Report these added fields in the console log of a machine check so that
  a record structure can be reconstituted from the console messages.
- Parse new architectural errors including memory controller errors.

MFC after:	1 week
2010-03-16 16:01:19 +00:00
jhb
a4d89c6f75 Use unsigned long long constants for fields in 64-bit machine check
registers instead of unsigned long constants.

MFC after:	3 days
2010-03-16 15:27:58 +00:00
mlaier
d62719cf37 Fix a small bug in drbr_dequeue_cond spotted while preparing MFC of r203834.
MFC after:	3 days
2010-03-15 21:15:03 +00:00
luigi
3ada53d651 small fixes to estimate the buffer size when requesting all pipes/flows. 2010-03-15 18:09:21 +00:00
luigi
3c242d0b3e + implement (two lines) the kernel side of 'lookup dscp N' to use the
dscp as a search key in table lookups;

+ (re)implement a sysctl variable to control the expire frequency of
  pipes and queues when they become empty;

+ add 'queue number' as optional part of the flow_id. This can be
  enabled with the command

        queue X config mask queue ...

  and makes it possible to support priority-based schedulers, where
  packets should be grouped according to the priority and not some
  fields in the 5-tuple.
  This is implemented as follows:
  - redefine a field in the ipfw_flow_id (in sys/netinet/ip_fw.h) but
    without changing the size or shape of the structure, so there are
    no ABI changes. On passing, also document how other fields are
    used, and remove some useless assignments in ip_fw2.c

  - implement small changes in the userland code to set/read the field;

  - revise the functions in ip_dummynet.c to manipulate masks so they
    also handle the additional field;

There are no ABI changes in this commit.
2010-03-15 17:14:27 +00:00
marcel
38cee4c837 Have cpu_throw() loop on blocked_lock as well. This bug has existed
a long time and has gone unnoticed just as long, because I kept
using sched_4bsd (due to sched_ule not working with preemption),
but GENERIC had sched_ule by default -- including SMP.

While here, remove unused inclusion of <machine/clock.h>, remove
totally bogus inclusion of <i386/include/specialreg.h>.
2010-03-15 16:53:09 +00:00
attilio
8a3325736a Make the code more readable and compiling on 64-bits arch different
than amd64.

Sponsored by:	Sandvine Incorporated
Submitted by:	emaste
MFC:		2 weeks
X-MFC:		r205160
2010-03-15 14:20:16 +00:00
nwhitehorn
dab875b1fd Fix two small bugs. The PowerPC 970 does not support non-coherent memory
access, and reflects this by autonomously writing LPTE_M into PTE entries.
As such, we should not panic if LPTE_M changes by itself. While here,
fix a harmless typo in moea64_sync_icache().
2010-03-15 00:27:40 +00:00
yongari
32eab59205 It seems PCI_OUR_REG_[1-5] registers are not mapped on PCI
configuration space on Yukon Ultra(88E8056) such that accesses to
these registers were NOPs which in turn make msk(4) instable on
this controller. Use indirect access method to access
PCI_OUR_REG_[1-5] registers. This should fix a long standing
instability bug which prevented msk(4) working on Yukon Ultra.
Special thanks to koitsu who gave me remote access to his system.

PR:	kern/114631, kern/116853
MFC after:	1 week
2010-03-14 23:23:57 +00:00
attilio
500e7d9ffd Checkin a facility for specifying a passthrough FIB from userland.
arcconf tool by Adaptec already seems to use for identifying the
Serial Number of the devices.
Some simple things (like FIB setup and bound checks) are retrieved
from the Adaptec's driver, but this implementation is quite different
because it does use the normal buffer dmat area for loading segments
and not a special one (like the Adaptec's one does).

Sponsored by:	Sandvine Incorporated
Discussed with:	emaste, scottl
Reviewed by:	emaste, scottl
MFC:		2 weeks
2010-03-14 22:38:18 +00:00
imp
40e45eec2f Go ahead and add USB support to the generic config. 2010-03-14 19:04:42 +00:00
rwatson
1fdd3bccc0 Abstract out initialization of most aspects of struct inpcbinfo from
their calling contexts in {IP divert, raw IP sockets, TCP, UDP} and
create new helper functions: in_pcbinfo_init() and in_pcbinfo_destroy()
to do this work in a central spot.  As inpcbinfo becomes more complex
due to ongoing work to add connection groups, this will reduce code
duplication.

MFC after:      1 month
Reviewed by:    bz
Sponsored by:   Juniper Networks
2010-03-14 18:59:11 +00:00
weongyo
d769d9f1e1 enables S/W beacon miss handler.
Reported by:	imp
2010-03-14 02:13:11 +00:00
weongyo
ca2c72ee9b fixes a broken software beacon miss handler. There is a race to check
vap->iv_bmiss_count == 0 in ieee80211_swbmiss because iv_swbmiss_task is
enqueued by taskqueue.

Reviewed by:	rpaulo
2010-03-14 01:57:32 +00:00
kmacy
b5dfb72f03 make UMA the default allocator for ZFS buffers - this avoids
a great deal of contention in kmem_alloc

MFC after:	7 days
2010-03-13 21:53:48 +00:00
kmacy
91efcb8e77 fix compilation under ZIO_USE_UMA 2010-03-13 21:52:21 +00:00
kmacy
cd0c2afd36 Don't bottleneck on acquiring the stream locks - this avoids a massive
drop off in throughput with large numbers of simultaneous reads

MFC after:	7 days
2010-03-13 21:41:52 +00:00
rnoland
7fd3bd147e Fix build after typo.
Reported by:	Sergey V. Dyatko <sergey.dyatko@gmail.com>
MFC after:	3 days
2010-03-13 18:14:51 +00:00
jkoshy
b4809b0e57 Correct a typo.
Submitted by:	Rahul Saxena <rahul dot k dot saxena at gmail dot com>
2010-03-13 15:10:07 +00:00
rnoland
9c66077065 Add support for Intel Pineview chips, aka IGD
Slightly modified version of the submitted patch.

PR:		143427
Submitted by:	Mamoru Sumida <msumida@mvc.biglobe.ne.jp>
MFC after:	3 days
2010-03-13 11:51:18 +00:00
ed
6cb70302d9 Remove COMPAT_43TTY from stock kernel configuration files.
COMPAT_43TTY enables the sgtty interface. Even though its exposure has
only been removed in FreeBSD 8.0, it wasn't used by anything in the base
system in FreeBSD 5.x (possibly even 4.x?). On those releases, if your
ports/packages are less than two years old, they will prefer termios
over sgtty.
2010-03-13 09:21:00 +00:00
jmallett
82f04b0d18 o) Use octeon_fpa_alloc_phys in a situation in which we don't need a usable
pointer, rather than octeon_fpa_alloc.
o) Report half duplex status properly.
o) Do not unconditionally update the last known link status in the softc.  If
   report_link isn't set, when octeon_rgmx_config_speed is called the first
   time it will tell the driver (essentially) that we have already marked the
   interface up.  Likewise, don't change media speed and duplex if only the
   link status is at issue. [1]
o) Remove manual changing of link state and let octeon_rgmx_config_speed do the
   heavy lifting. [1]

Reviewed by:	[1] imp
Sponsored by:	Packet Forensics
2010-03-13 04:55:47 +00:00
rrs
5db64758fc The proper fix for the delayed SCTP checksum is to
have the delayed function take an argument as to the offset
to the SCTP header. This allows it to work for V4 and V6.
This of course means changing all callers of the function
to either pass the header len, if they have it, or create
it (ip_hl << 2 or sizeof(ip6_hdr)).
PR:		144529
MFC after:	2 weeks
2010-03-12 22:58:52 +00:00
ticso
2e508fb884 fix type in comment 2010-03-12 22:39:35 +00:00
rnoland
84a4152445 Add support of Intel Pineview chips, aka IGD.
MFC after:	3 days
2010-03-12 21:34:23 +00:00
kmacy
a5e0110227 flowtable_get_hashkey is only used by a DDB function - move under #ifdef DDB
pointed out by jkim@
2010-03-12 19:58:51 +00:00
rnoland
de23516bf1 Add pci ids for Intel Ironlake chipsets.
These behave just like g45 for agp.

Tested by:	Torfinn Ingolfsen

MFC after:	3 days
2010-03-12 19:43:39 +00:00
jkim
5e802872af Fix a style(9) nit. 2010-03-12 19:42:42 +00:00
kmacy
965730af4f re-update copyright to 2010
pointed out by danfe@
2010-03-12 19:26:45 +00:00
jkim
df5e72589a Tidy up callout for select(2) and read timeout.
- Add a missing callout_drain(9) before the descriptor deallocation.[1]
- Prefer callout_init_mtx(9) over callout_init(9) and let the callout
subsystem handle the mutex for callout function.

PR:		kern/144453
Submitted by:	Alexander Sack (asack at niksun dot com)[1]
MFC after:	1 week
2010-03-12 19:14:58 +00:00