Commit Graph

254 Commits

Author SHA1 Message Date
Tycho Nightingale
ae45750d6c Improve the ability to cancel an in-flight request by using an
interrupt, via SIGCONT, to force the read or write system call to
return prematurely.

Reviewed by:	grehan
2014-11-04 01:06:33 +00:00
Tycho Nightingale
26bf96112b If the start bit, PxCMD.ST, is cleared and nothing is in-flight then
PxCI, PxSACT, PxCMD.CCS and PxCMD.CR should be 0.

Reviewed by:	grehan
2014-11-03 12:55:31 +00:00
Neel Natu
c17d4a83b8 Add a comment explaining the intent behind the I/O reservation [0x72-0x77]. 2014-10-26 21:17:44 +00:00
Neel Natu
160ef77abf Move the ACPI PM timer emulation into vmm.ko.
This reduces variability during timer calibration by keeping the emulation
"close" to the guest. Additionally having all timer emulations in the kernel
will ease the transition to a per-VM clock source (as opposed to using the
host's uptime keep track of time).

Discussed with:	grehan
2014-10-26 04:44:28 +00:00
Neel Natu
e1a172e1c2 IFC @r273214 2014-10-20 02:57:30 +00:00
Neel Natu
592cd7d3be Don't advertise the "OS visible workarounds" feature in cpuid.80000001H:ECX.
bhyve doesn't emulate the MSRs needed to support this feature at this time.

Don't expose any model-specific RAS and performance monitoring features in
cpuid leaf 80000007H.

Emulate a few more MSRs for AMD: TSEG base address, TSEG address mask and
BIOS signature and P-state related MSRs.

This eliminates all the unimplemented MSRs accessed by Linux/x86_64 kernels
2.6.32, 3.10.0 and 3.17.0.
2014-10-19 21:38:58 +00:00
Tycho Nightingale
3ef05c4677 Support stopping and restarting the AHCI command list via toggling
PxCMD.ST from '1' to '0' and back.  This allows the driver a chance to
recover if for instance a timeout occurred due to activity on the
host.

Reviewed by:	grehan
2014-10-17 11:37:50 +00:00
Neel Natu
2688a818a3 Don't advertise the Instruction Based Sampling feature because it requires
emulating a large number of MSRs.

Ignore writes to a couple more AMD-specific MSRs and return 0 on read.

This further reduces the unimplemented MSRs accessed by a Linux guest on boot.
2014-10-17 06:23:04 +00:00
Neel Natu
02904c45ab Hide extended PerfCtr MSRs on AMD processors by clearing bits 23, 24 and 28 in
CPUID.80000001H:ECX.

Handle accesses to PerfCtrX and PerfEvtSelX MSRs by ignoring writes and
returning 0 on reads.

This further reduces the number of unimplemented MSRs hit by a Linux guest
during boot.
2014-10-17 03:04:38 +00:00
Neel Natu
913d54b96e Emulate the "Hardware Configuration" MSR when running on an AMD host.
This gets rid of the "TSC doesn't count with P0 frequency!" message when
booting a Linux guest.

Tested on an "AMD Opteron 6320" courtesy of Ben Perrault.
2014-10-16 19:27:26 +00:00
Neel Natu
ed6aacb51f IFC @r272887 2014-10-10 23:52:56 +00:00
Neel Natu
5295c3e61d Support Intel-specific MSRs that are accessed when booting up a linux in bhyve:
- MSR_PLATFORM_INFO
- MSR_TURBO_RATIO_LIMITx
- MSR_RAPL_POWER_UNIT

Reviewed by:	grehan
MFC after:	1 week
2014-10-09 19:13:33 +00:00
Neel Natu
02c282e862 iasl(8) expects integer fields in data tables to be specified as hexadecimal
values. Therefore the bit width of the "PM Timer Block" was actually being
interpreted as 50-bits instead of the expected 32-bit.

This eliminates an error message emitted by a Linux 3.17 guest during boot:
"Invalid length for FADT/PmTimerBlock: 50, using default 32"

Reviewed by:	grehan
MFC after:	1 week
2014-10-09 19:02:32 +00:00
Neel Natu
8ccb28efcd Implement the FLUSH operation in the virtio-block emulation.
This gets rid of the following error message during FreeBSD guest bootup:
"vtbd0: hard error cmd=flush fsbn 0"

Reported by:	rodrigc
Reviewed by:	grehan
2014-10-07 17:08:53 +00:00
Neel Natu
107af8f2ed IFC @r272481 2014-10-05 01:28:21 +00:00
Peter Grehan
8b58e6af3c Add new fields in the FADT, required by IASL 20140926-64.
The new IASL from the recent acpi-ca import will error out
if it doesn't see these new fields, which were previously
reserved.

Reported by:	lme
Reviewed by:	neel
2014-10-03 17:27:30 +00:00
Neel Natu
970388bf8d IFC @r272185 2014-09-27 22:15:50 +00:00
Peter Grehan
5ed6ab5baa Correct display of bhyve SMBIOS UUIDs with dmidecode by bumping the version.
The mixed little/big-endianness of SMBIOS UUIDs was clarified in v2.6
of the SMBIOS spec. dmidecode uses the reported version of SMBIOS to
determine the layout and what to byte-swap.

bhyve's SMBIOS reported as 2.4 though it implemented the 2.6-style of
memory layout. This resulted in dmidecode reporting a different
UUID than one passed in via the -U option.

Fix by exporting a version of 2.6.

Reviewed by:	tychon
Reported by:	julian
MFC after:	1 day
2014-09-23 01:17:22 +00:00
Neel Natu
8f02c5e456 IFC r271888.
Restructure MSR emulation so it is all done in processor-specific code.
2014-09-20 21:46:31 +00:00
Neel Natu
b6cf6c8ca6 IFC @r271887 2014-09-20 06:27:37 +00:00
Neel Natu
c3498942a5 Restructure the MSR handling so it is entirely handled by processor-specific
code. There are only a handful of MSRs common between the two so there isn't
too much duplicate functionality.

The VT-x code has the following types of MSRs:

- MSRs that are unconditionally saved/restored on every guest/host context
  switch (e.g., MSR_GSBASE).

- MSRs that are restored to guest values on entry to vmx_run() and saved
  before returning. This is an optimization for MSRs that are not used in
  host kernel context (e.g., MSR_KGSBASE).

- MSRs that are emulated and every access by the guest causes a trap into
  the hypervisor (e.g., MSR_IA32_MISC_ENABLE).

Reviewed by:	grehan
2014-09-20 02:35:21 +00:00
Neel Natu
4e27d36d38 IFC @r271694 2014-09-17 18:46:51 +00:00
Glen Barber
7fca1ad503 Update the bhyve(8) manual to reflect that it is no
longer considered 'experimental.'

Reviewed by:	grehan
MFC after:	3 days
Sponsored by:	The FreeBSD Foundation
2014-09-17 16:45:20 +00:00
Neel Natu
bbadcde418 Set the 'vmexit->inst_length' field properly depending on the type of the
VM-exit and ultimately on whether nRIP is valid. This allows us to update
the %rip after the emulation is finished so any exceptions triggered during
the emulation will point to the right instruction.

Don't attempt to handle INS/OUTS VM-exits unless the DecodeAssist capability
is available. The effective segment field in EXITINFO1 is not valid without
this capability.

Add VM_EXITCODE_SVM to flag SVM VM-exits that cannot be handled. Provide the
VMCB fields exitinfo1 and exitinfo2 as collateral to help with debugging.

Provide a SVM VM-exit handler to dump the exitcode, exitinfo1 and exitinfo2
fields in bhyve(8).

Reviewed by:	Anish Gupta (akgupt3@gmail.com)
Reviewed by:	grehan
2014-09-14 04:39:04 +00:00
Neel Natu
1aba8e7ff8 Initialize 'bc_rdonly' to the right value.
Note that independent of this change a readonly disk file would still be
opened O_RDONLY and protected from writes by the guest.

Reviewed by:	grehan
2014-09-11 21:15:20 +00:00
Peter Grehan
82560f19d0 Allow vtnet operation without merged rx buffers.
NetBSD's virtio-net implementation doesn't negotiate
the merged rx-buffers feature. To support this, check
to see if the feature was negotiated, and then adjust
the operation of the receive path accordingly by using
a larger iovec, and a smaller rx header.
In addition, ignore writes to the (read-only) status byte.

Tested with NetBSD/amd64 5.2.2, 6.1.4 and 7-beta.

Reviewed by:	neel, tychon
Phabric:	D745
MFC after:	3 days
2014-09-09 22:35:02 +00:00
Peter Grehan
e18f344b9b Add a callback to be notified about negotiated features.
Submitted by:	luigi
Obtained from:	Vincenzo Maffione, Universita` di Pisa
MFC after:	3 days
2014-09-09 04:11:54 +00:00
Neel Natu
04da7226c4 Set the 'inst_length' to '0' early on before any error conditions are detected
in the emulation of the task switch. If any exceptions are triggered then the
guest %rip should point to instruction that caused the task switch as opposed
to the one after it.
2014-08-30 18:35:16 +00:00
Tycho Nightingale
b297e71ede Fix a recursive lock acquisition in vi_reset_dev().
Reviewed by:	grehan
2014-08-22 13:01:22 +00:00
Neel Natu
33424543f2 Minor cleanup:
- Set 'pirq_cold' to '0' on the first PIRQ allocation.
- Make assertions stronger.

Reviewed by:	jhb
CR:		https://phabric.freebsd.org/D592
2014-08-13 00:14:26 +00:00
Neel Natu
12a6eb99a1 Support PCI extended config space in bhyve.
Add the ACPI MCFG table to advertise the extended config memory window.

Introduce a new flag MEM_F_IMMUTABLE for memory ranges that cannot be deleted
or moved in the guest's address space. The PCI extended config space is an
example of an immutable memory range.

Add emulation for the "movzw" instruction. This instruction is used by FreeBSD
to read a 16-bit extended config space register.

CR:		https://phabric.freebsd.org/D505
Reviewed by:	jhb, grehan
Requested by:	tychon
2014-08-08 03:49:01 +00:00
Tycho Nightingale
42404fae46 Commands which encounter a fatal error shouldn't be marked as completed.
Furthermore, provide an indication of the current command so it can be
determined which one actually failed.

Reviewed by:	grehan
2014-07-30 18:47:31 +00:00
Neel Natu
afd5e8ba88 Simplify the meaning of return values from the inout handlers. After this
change 0 means success and non-zero means failure.

This also helps to eliminate VMEXIT_POWEROFF and VMEXIT_RESET as return values
from VM-exit handlers.

CR:		D480
Reviewed by:	grehan, jhb
2014-07-25 20:18:35 +00:00
Neel Natu
e84d8ebfcc Reduce the proliferation of VMEXIT_RESTART in task_switch.c.
This is in preparation for further simplification of the return values from
VM exit handlers in bhyve(8).
2014-07-24 05:31:57 +00:00
Neel Natu
d37f2adb38 Fix fault injection in bhyve.
The faulting instruction needs to be restarted when the exception handler
is done handling the fault. bhyve now does this correctly by setting
'vmexit[vcpu].inst_length' to zero so the %rip is not advanced.

A minor complication is that the fault injection APIs are used by instruction
emulation code that is shared by vmm.ko and bhyve. Thus the argument that
refers to 'struct vm *' in kernel or 'struct vmctx *' in userspace needs to
be loosely typed as a 'void *'.
2014-07-24 01:38:11 +00:00
Neel Natu
d665d229ce Emulate instructions emitted by OpenBSD/i386 version 5.5:
- CMP REG, r/m
- MOV AX/EAX/RAX, moffset
- MOV moffset, AX/EAX/RAX
- PUSH r/m
2014-07-23 04:28:51 +00:00
Neel Natu
091d453222 Handle nested exceptions in bhyve.
A nested exception condition arises when a second exception is triggered while
delivering the first exception. Most nested exceptions can be handled serially
but some are converted into a double fault. If an exception is generated during
delivery of a double fault then the virtual machine shuts down as a result of
a triple fault.

vm_exit_intinfo() is used to record that a VM-exit happened while an event was
being delivered through the IDT. If an exception is triggered while handling
the VM-exit it will be treated like a nested exception.

vm_entry_intinfo() is used by processor-specific code to get the event to be
injected into the guest on the next VM-entry. This function is responsible for
deciding the disposition of nested exceptions.
2014-07-19 20:59:08 +00:00
Neel Natu
3d5444c864 Add emulation for legacy x86 task switching mechanism.
FreeBSD/i386 uses task switching to handle double fault exceptions and this
change enables that to work.

Reported by:	glebius
2014-07-16 21:26:26 +00:00
Peter Grehan
ad15140ee7 Use the blockif CHS routine to create fake CHS values,
and then populate them in the identity page.

This fixes a divide-by-zero error at probe time with NetBSD.

MFC after:	1 week.
2014-07-15 00:27:08 +00:00
Peter Grehan
c4813fadf1 Add a call to synthesize a C/H/S value for block emulations
that require it (ahci). The algorithm used is from the VHD
specification.
2014-07-15 00:25:54 +00:00
Peter Grehan
18e32ebc89 Extend capabilities to 64-bits in preparation for some API changes.
The v1.0 virtio spec supports an extended size for guest/host
caps, but in practice 64-bits should last for a long time.
2014-07-05 02:38:53 +00:00
Peter Grehan
f23a8ac1b9 Use correct flag for event index.
Submitted by:	luigi
Obtained from:	Vincenzo Maffione, Universita` di Pisa
MFC after:	1 week
2014-07-03 00:23:14 +00:00
Neel Natu
64fe72354c Add post-mortem debugging for "EPT Misconfiguration" VM-exit. This error
is hard to reproduce so try to collect all the breadcrumbs when it happens.

Reviewed by:	grehan
2014-06-27 18:00:38 +00:00
John Baldwin
cde1f5b8a0 Sort command flags in usage output and the manpages. 2014-06-27 15:20:34 +00:00
Peter Grehan
62f17e92fe Set the version and date to fixed fields rather than using
preprocessor macros that don't allow reproducible builds.
As a side-effect, the date string is now spec-compliant.

root@bhyve:~ # dmidecode
# dmidecode 2.12
SMBIOS 2.4 present.
12 structures occupying 514 bytes.
Table at 0x000F101F.

Handle 0x0001, DMI type 0, 24 bytes
BIOS Information
        Vendor: BHYVE
        Version: 1.0
        Release Date: 03/14/2014

Submitted by:	des (original version)
Reviewed by:	tychon
MFC after:	1 week
2014-06-27 05:27:37 +00:00
John Baldwin
5749449d9b - Document -b to enable the bvmcons console (but mark it as deprecated
similar to -g.)
- Document -U to set the SMBIOS UUID.
- Add missing options to the usage output and to the manpage Synopsis.
- Don't claim that bvmdebug is amd64-only (it is also a device, not an
  option).
2014-06-26 20:12:38 +00:00
Neel Natu
be679db4cd Provide APIs to directly get 'lowmem' and 'highmem' size directly.
Previously the sizes were inferred indirectly based on the size of the mappings
at 0 and 4GB respectively. This works fine as long as size of the allocation is
identical to the size of the mapping in the guest's address space. However, if
the mapping is disjoint then this assumption falls apart (e.g., due to the
legacy BIOS hole between 640KB and 1MB).
2014-06-24 02:02:51 +00:00
Baptiste Daroussin
01c2b8ac0d use .Mt to mark up email addresses consistently (part2)
PR:		191174
Submitted by:	Franco Fichtner  <franco@lastsummer.de>
2014-06-20 09:57:27 +00:00
Neel Natu
79aad80d3c Fix typo and rename macro KDB_SYS_FLAG to KBD_SYS_FLAG.
Reviewed by:	tychon
2014-06-18 17:20:02 +00:00
Tycho Nightingale
67b6ffaad6 r267169 should apply to 64-bit BARs as well.
Reviewed by:	neel
2014-06-09 19:55:50 +00:00