Commit Graph

619 Commits

Author SHA1 Message Date
adrian
b9966c9f48 This was missing from the previous HAL commit - it fixes a typo and
introduces the PS-POLL hardware support.
2011-03-26 11:59:18 +00:00
adrian
030940dad5 If 802.11n is enabled, bump the number of buffers used up to a larger
level.

This is important for AMPDU RX as each burst is multiple packets in a row.
2011-03-26 11:58:29 +00:00
adrian
4f32c1a13f Add in the hardware PS-POLL frame reception setting, but leave it disabled
by default.

Adventourous souls with an AR9220/AR9280 or later and who have a device
that sends PS-POLL frames may wish to try tinkering with this option and
get back to me.
2011-03-26 10:52:37 +00:00
adrian
66cc5279f5 Introduce hardware PS-POLL support in the HAL.
Linux ath9k only enables this for AR9280 and later NICs; so
create a capability for it so it isn't enabled for earlier
NICs.

Enabling hardware PS-POLL support will come in a later commit
and will be disabled by default.
2011-03-26 10:47:17 +00:00
adrian
f67f722dc8 Put these two back to mirror what ath9k does.
Even though they map to setting the error filter register,
ath9k also writes them untouched to AR_RX_FILTER.

The Force-BSSID match bit can stay high, as it maps to a
misc mode register setting rather than an RX filter bit.
2011-03-26 07:29:48 +00:00
adrian
45abd9f4f2 Shuffle around the HAL_RX_FILTER bits to be slightly more sensible.
The phyerr, radar and bssid-match bits aren't real bits, they map
to enabling bits in other registers. Move those out of the way of
valid RX filter bits.

Add a few new fields from ath9k - compba, ps-poll, mcast-bcast-all.
2011-03-26 07:15:35 +00:00
adrian
3fa8d0321a After discussing with Bernhard, the "right" way in net80211 to check
the channel width is ni->ni_chw, which is set to the negotiated channel
width. ni->ni_htflags is the capability, rather than the negotiated
value.

Teach both the TX path and the sample rate module about this.
2011-03-25 10:55:25 +00:00
adrian
4b79add9d6 I broke periodic adc calibrations - so restore them to working order. 2011-03-25 10:53:13 +00:00
adrian
44a57e35ff Re-disable the setting of 2040/shortgi bits for now.
This seems to work fine for STA but not HT/20 AP mode.

Further discussion with net80211 people will need to take place
to ensure that the right flags are set based on the negotiated
capabilities of the remote peer, rather than whatever the local
parameters are.

Sending short-gi frames in 20mhz may work on some chips but
it certainly isn't supported on anything currently supported
by the HAL; and sending HT40 frames in HT20 mode just plain
won't work.
2011-03-25 04:15:30 +00:00
adrian
e4f893f2cf After discussion with Felix Fietkau (nbd) about the ath9k Merlin LNA bit
settings, it seems that our defines are backwards and don't match what
is in the EEPROM documentation or internal driver.

The ath9k code used to have a bitfield here, rather than a uint8_t, and
there were #defines used to swap the order based on the endian of the
platform - this wasn't because of nybble or bit ordering of the
underlying host but because of what the compiler was doing.

This may be the reason for the backwards field numbers, as ath9k had
similar issues.
2011-03-25 00:45:24 +00:00
adrian
e58905010c Flip ANI on for the AR5416 and later chips. I haven't verified it on
the AR9285 so I'll leave it off for that.

Ath9k sources indiciate that one of the ANI modes interferes with
RIFS detection, so match ath9k and disable that.
2011-03-25 00:40:08 +00:00
adrian
6fa5e5cfe1 The right commit - add a couple more AR_PCU_MISC_MODE2 register bits -
SOWL specific.
2011-03-25 00:06:58 +00:00
adrian
a64bc82d66 oops, commited the wrong file change. 2011-03-25 00:06:19 +00:00
adrian
1e585edb44 Add some more AR_PCU_MISC_MODE2 register settings - these are SOWL or later. 2011-03-25 00:05:26 +00:00
adrian
4051a05f56 Bring over interrupt mitigation changes from ath9k.
* The existing interrupt mitigation code didn't mitigate anything - the
  per-packet TX/RX interrupts are still occuring. It's possible this
  worked for the AR5416 but not any later chipsets; I'll investigate and
  update as needed.

* Set both the RX and TX threshold registers whilst I'm at it.

This is verified to work on the AR9220 and AR9160. I'm leaving it off
by default in case it's truely broken, but I need to have it enabled
when doing 11n testing or interrupt loads exceed 10,000 interrupts/sec.
2011-03-25 00:03:21 +00:00
adrian
9072e106a9 Flip back HT/40 and Short-GI (for 40mhz operation). These are now verified to work. 2011-03-24 16:06:54 +00:00
adrian
bedd483b34 Fix a completely wrong variable reference. 2011-03-24 04:57:35 +00:00
adrian
8427bd698c Make the ar2133ForceBias() call controllable at runtime.
At least one AR5416 user has reported measurable throughput drops
with this option. For now, disable it and make it a run-time
twiddle. It won't take affect until the next radio programming
trip though (eg channel scan, channel change.)
2011-03-23 23:48:44 +00:00
adrian
7ae3cbd3a0 The AR5416+ chips all have MIB counters (which the AR5416 ANI code assumes)
so there's no need to enable the RX of invalid frames just to do ANI.

The if_ath code and AR5212 ANI code setup the RX filter bits to enable
receiving OFDM/CCK errors if the device doesn't have the hardware
MIB counters. It isn't initialising it for the AR5416+ because all of
those chips have hardware MIB counters.

This fixes the odd (and performance affecting!) situation where if ani
is enabled (via sysctl dev.ath.X.intmit) then suddenly there's be a very
large volume of phy errors - which is good to track, but not what was
intended. Since each PHY error is a received (0 length) frame, it can
significantly tie up the RX side of things.
2011-03-23 03:58:55 +00:00
adrian
168b5df398 Enable setting the MCS rate bit for ast_tx_rate.
This allows ath_stats to print the MCS rate when TX'ing.
2011-03-22 22:59:09 +00:00
adrian
8b14a81753 Clean up setting the short preamble bit in the rate - this way it
is very obvious (and cleanly so) that it occurs for non-11n rates.
2011-03-22 13:39:00 +00:00
adrian
bf0192385b Flip this over to be a configurable option for people who wish to play with it.
It's still not ready for prime-time - there's some TX niggles with these 11n
cards that I'm still trying to wrap my head around, and AMPDU-TX is just not
implemented so things will come to a crashing halt if you're not careful.
2011-03-22 13:35:56 +00:00
adrian
3533e9348f This isn't actually needed any longer, A-MPDU frames work fine if only tagged for 11n nodes. 2011-03-22 13:20:11 +00:00
adrian
06d8daf5f3 Bring over an XPA (external power amplifer) bias fix for the AR9160.
This fix modifies the const addac initval array, rather than modifying
a local copy. It means that running >1 AR9160 on a board may prove to
be unpredictable.

The AR5416 init path also does something similar, so supporting
>1 AR5416 of different revisions could cause problems.

The later fix will be to create a private copy of the Addac data
for the AR5416, AR9160 (and AR9100 when it's merged in) and then
modify that as needed.

Obtained From:	Linux ath9k
2011-03-22 10:29:36 +00:00
adrian
0bc8dc6ea4 Fix OFDM ANI statistics gathering for the AR5416 and later chips.
I found this when trying to figure out why the RX PHY error count
didn't match the OFDM error count ANI was using. It turns out
there was two problems:

* What this commit addresses - using the wrong mask for OFDM errors,
  and
* The RX filter is set incorrectly after a channel scan (at least)
  even if interference mitigation is enabled by default.

ANI is still disabled by default for the AR5416 and later chips.
2011-03-22 07:19:49 +00:00
adrian
9d9da16337 Set the "right" CCA register.
Obtained From:	ath9k
2011-03-22 05:47:48 +00:00
adrian
57d3996c32 Break out the RF mode setup into ar5416SetRfMode(), mirroring what ath9k does. 2011-03-22 00:52:44 +00:00
adrian
2a5d8fbd5e Do a bit of spring cleaning in the board setup code, just to
bring it in line with the rest of the register initialisation.

I've verified that the 2/5ghz board values written to the
chip match what was previously written.
2011-03-22 00:43:58 +00:00
adrian
ce1da40e3d Bring over a few queue changes from ath9k:
* add pspoll/uapsd queue setup defaults;
* enable the exponential backoff window rather than the random
  backoff window when doing TX contention management.
2011-03-22 00:14:17 +00:00
adrian
f7f4efa2a0 Even though it's very unlikely the misc mode register setting at -attach-
would be a problem, make sure it isn't overwritten by whatever is in
there at cold reset.

This brings the > ar5416 init path treatment of AR_MISC_MODE.
2011-03-22 00:12:26 +00:00
adrian
e204f119d9 Remove the merlin delay workaround here, it isn't appropriate for
the analog bank writes as Merlin never does them.
2011-03-22 00:11:04 +00:00
adrian
8a3060a483 Back that commit out - something's broken, and I need to figure out
what/why.
2011-03-21 17:44:52 +00:00
adrian
4f9afc394f This CLKDRV workaround should only be for AR5416 v2.0/2.1;
the check was too strict and enabled it for all non AR5416-v2.2
chipsets - including later ones.
2011-03-21 17:12:03 +00:00
adrian
46e21ba9ec Fix static ucastrate for ath_rate_sample.
* Pull out the static rix stuff into a different function
* I know this may slightly drop performance, but check if a static
  rix is needed before each packet TX.

* Whilst I'm at it, add a little extra debugging to the rate
  control stuff to make it easier to follow what's going on.
2011-03-21 12:51:13 +00:00
adrian
6d1f9b3ed0 Disable a check I added a while ago to ensure the initial NF cal completed.
Give it a good go (32 attempts) and then print out a warning that's
going to occur whether HAL debugging is enabled or not. Then don't
abort the radio setup; just continue merrily along.

This should fix the issue that users were having where scanning would
occasionally fail on the active channel, causing traffic to cease
until the radio scanned again.
2011-03-20 15:46:05 +00:00
adrian
133a80d1fd Cave in and disable the ADC DC gain/offset calibrations if they're
not needed.

These calibrations are only applicable if the chip operating mode
engages both interleaved RX ADCs (ie, it's compensating for the
differences in DC gain and DC offset -between- the two ADCs.)
Otherwise the chip reads values of 0x0 for the secondary ADC
(as I guess it's not enabled here) and thus writes potentially
bogus info into the chip.

I've tested this on the AR9160 and AR9280; both behave themselves
in 11g mode with these calibrations disabled.
2011-03-20 09:08:45 +00:00
adrian
64679243da * Remove a not-needed check in the AR5416+ case
* Restore the chip default of the DCU backoff threshold to 0x2,
  mirroring what ath9k does.
2011-03-20 08:47:59 +00:00
adrian
3923f7a93d Bring over a copy of the AR5212 TX queue reset and setup routines, in preparation
for fixing them based on the ath9k related TXQ fixes.

I've done this so people can go over the history of the diffs to the original
AR5212 routines (which AR5416 and later chips use) to see what's changed.
2011-03-20 08:42:56 +00:00
adrian
2066f0592e Add a PSPOLL queue type, in preparation for (eventually) porting
over the TX queue setup code from ath9k for the AR5416 and later
chips.
2011-03-20 08:27:06 +00:00
adrian
f12f2f2a3d Add in the channel survey data structures. These will be filled out
by the HAL at some point in the future.
2011-03-19 14:38:28 +00:00
adrian
4483667ac9 Reserve a new diagnostic code for the channel survey code I'll add soon. 2011-03-19 14:37:13 +00:00
adrian
e85dde4087 Make sure that the AR_MISC_MODE value from the initvals are properly respected.
This commit really is "fix the OFDM duration calculation to match reality when
running in 802.11g mode."

The AR5212 init vals set AR_MISC_MODE to 0x0 and all the bits that can be set are
set through code.

The AR5416 and later initvals set AR_MISC_MODE to various other values (with
the AR5212 AR_MISC_MODE options cleared), which include AR_PCU_CCK_SIFS_MODE .
This adds 6uS to SIFS on non-CCK frames when transmitting.

This fixes the issue where _DATA_ 802.11g OFDM frames were being TX'ed with
the ACK duration set to 38uS, not 44uS as on the AR5212 (and other devices.)

The AR5212 TX pathway obeys the software-programmed duration field in the packet,
but the 11n TX pathway overrides that with a hardware-calculated duration. This
was getting it wrong because of the above AR_MISC_MODE setting. I've verified
that 11g data OFDM frames are now being TXed with the correct ACK+SIFS duration
programmed in.
2011-03-19 03:15:28 +00:00
adrian
895978da06 Use the HAL method rather than directly calling ar5212ResetTxQueue().
Since ath9k does some slightly different bit fiddling when setting up
the TX queues, it may that the TX queue setup/reset functions will need
overriding later on.
2011-03-19 03:09:21 +00:00
adrian
483d4d7b61 Add debugging messages to the AR5416 ANI code that's found in the AR5212 ANI code. 2011-03-19 00:46:10 +00:00
adrian
14578a642c Fix typo that snuck in. 2011-03-14 02:32:10 +00:00
adrian
5308dd1598 Bring over the AR9285 board update code from ath9k.
This does a few things in particular:

* Abstracts out the gain control settings into a separate function;
* Configure antenna diversity, LNA and antenna gain parameters;
* Configure ob/db entries - the later v4k EEPROM modal revisions have
  multiple OB/DB parameters which are used for some form of
  calibration. Although the radio does have defaults for each,
  the EEPROM can override them.

This resolves the AR2427 related issues I've been seeing and makes
it stable at all 11g rates for both TX and RX.
2011-03-14 00:42:48 +00:00
adrian
f90fad94e2 Fix the nfarray offsets for the ar2133/ar5133 radio - (AR5416, AR9160, etc.)
The offsets didn't match the assumption that nfarray[] is ordered by the
chainmask bits and programmed via the register order in ar5416_cca_regs[].
This repairs that damage and ensures that chain 1 is programmed correctly.
(And extension channels will now be programmed correctly also.)

This fixes some of the stuck beacons I've been seeing on my AR9160/AR5416
setups - because Chain 1 would be programmed -80 or -85 dBm, which is
higher than the actual noise floor and thus convincing the radio that
indeed it can't ever transmit.
2011-03-13 13:00:45 +00:00
adrian
5e36ae5370 The number of streams is not based on the interface stream count, but the
number of streams needed for that MCS rate.
2011-03-13 08:23:59 +00:00
adrian
64cd31ce69 Move out some of the shared eeprom board value calculation routines into ah.c
rather than duplicating them for the v14 (ar5416+) and v4k (ar9285) codebases.

Further chipsets (eg the AR9287) have yet another EEPROM format which will use
these routines to calculate things.
2011-03-13 05:54:05 +00:00
adrian
d4ef3ac078 * Add in some board settings debugging to log what's being written
to the TX closed-loop power control registers.
* Modify a couple of functions to take the register chain number,
  rather than the regChainOffset value. This allows for the
  register chain to be logged.
2011-03-13 05:30:14 +00:00