switch reset/initialise functions.
The AR934x and QC955x SoCs both have a configurable MDIO base clock.
The others have the MDIO clock use the same clock as the system
reference clock, whatever that may be.
Tested:
* AR9344 SoC
TODO:
* mips24k - AR933x would be fine for now, just to ensure that things
are sane.
control block.
The GMAC configuration block allows for some configuration of how
the GMAC0 (ie, arge0) port is connected to the on-board switch
(if indeed there is one.) It both can be pushed into the on-board
switch; it could also be torn out and exposed via an external
MII (and that operational mode is also controllable.)
Obtained from: Linux/OpenWRT
add some packet(s) to tx ring and arge_stop() is called before receive the
sent packet interrupt from hardware. Fix arge_stop() to unload the in use
dma tags and free the associated mbuf.
PR: 178319, 163670
Approved by: adrian (mentor)
(re)start the interface when it is down. This change fix a race with
BOOTP where the response packet is lost because the interface is being
reset by a netmask change right after send the packet.
PR: 178318
Approved by: adrian (mentor)
form xx:xx:xx:xx:xx:xx complete with ":" characters taking of 18 bytes
instead of 6 integers. Expose a "readascii" tuneable to handle this case.
Remove restriction on eepromac assignement for the first dev instance only.
Add eepromac address for DIR-825 to hints file.
Add readascii hint for DIR-825
Reviewed by: adrian@
This code reads the PLL configuration registers and correctly programs
things so the UART and such can come up.
There's MIPS74k platform issues that need fixing; but this at least brings
things up enough to echo stuff out the serial port and allow for interactive
debugging with ddb.
Tested:
* AR71xx SoCs
* AR933x SoC
* AR9344 board (DB120)
Obtained from: Qualcomm Atheros; Linux/OpenWRT
For all pre-AR933x chips, the frequency is just the APB frequency.
For the AR933x, the UART frequency is different but we just hacked around
it.
For the AR934x, there's a different PLL setting for these, so they have
to be broken out.
sys/arm and sys/mips), squelching the clang 3.3 warnings about this.
Noticed by: tinderbox and many irate spectators
Submitted by: Luiz Otavio O Souza <loos.br@gmail.com>
PR: kern/177759
MFC after: 3 days
* Enable RX and host interrupts during bus probe/attach
* Disable all interrupts (+ host ISR) during bus detach
* Enable TX DONE interrupt only when we start transmitting; clear it when
we're done.
* The RX/TX FIFO depth is still conjecture on my part. I'll fix this
shortly.
* The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty"
interrupt. Sigh. So..
* .. in ar933x_bus_transmit(), wait for the FIFO to drain before
continuing.
I dislike having to wait for the FIFO to drain, alas.
Tested:
* Atheros AP121 board, AR9331 SoC.
TODO:
* RX/TX overflow, RX error, BREAK support, etc.
* Figure out the true RX/TX FIFO depth.
This implements the bus transmit/receive/sigchg/ipend methods with
a polled interrupt handler (ipend) rather than enabling hardware
interrupts.
The FIFO is faked at 16 bytes deep for now, just so the transmit
IO side doesn't suck too bad (the callout frequency limits how quickly
IO is flushed to the sender, rather than scheduling the callout more
frequently whilst there's active TX. But I digress.)
Tested:
* Atheros AP121 (AR9330) reference board, booting to multi-user interactive
mode.
* Add baud rate and divisor programming code. See below for more
information.
* Flesh out ar933x_init() to disable interrupts and program the initial
console setup.
* Remove #if 0'ed code from ar933x_term().
* Explain what these functions do.
Now, the baud rate and divisor code comes from Linux, as a submission
to the OpenWRT project and Linux kernel from
Gabor Juhos <juhosg@openwrt.org>.
The original ticket for this code is https://dev.openwrt.org/ticket/12031 .
I've contacted Gabor and asked for his permission to also licence the patch
in question (which covers this code) to BSD lience and he's agreed.
Hence why I'm including it here in FreeBSD.
Tested:
* AP121 (AR9330)
* Default clock is 25MHz;
* Remove the UART register macro here - it's not needed as we don't need
to "adjust" the register offset / spacing at all;
* Remove unused fields in the softc.
Tested:
* AP121
This implements the kernel glue needed (getc, putc, rxready).
This isn't a 16550 UART, even if the datasheet overview claims so.
The Linux ar933x support was used as a reference, however the uart code
is a reimplementation.
Attentive viewers will note that the uart code is based off of the ns8250
code and the UART bus code is a stubbed-out version of this. I'll be
replacing it with non-stubbed versions soon, making this a fully featured
driver.
Tested:
* AP121 reference board (AR933x), booting through the mountroot> prompt;
then doing some basic interactive tests in ddb.
This was ported from the AR724x code and I think that also doesn't
quite work. I'll investigate that soon.
With this in place the system reset path works, so 'reset' from kdb
actually resets the SoC.
Tested:
* AP121 test board
CPUs.
The AR933x is a mips24k based SoC with an AR9380 series SoC on board,
two gigabit ethernet interfaces and an internal 10/100mbit ethernet
switch. There's also the normal interfaces (USB, ethernet, uart, GPIO.)
The downside? There's a non-ns8250 UART device.
With a very basic UART driver (not in this commit) the SoC is initialised
and boots up. I'll commit the UART code soon and then link it into the
general setup path.
This code is a re-implementation based from the Linux kernel / openwrt
AR933x support.
TODO:
* UART (obviously)
* All of the ethernet, USB and wifi SoC glue, including ethernet PLL
programming.
* Mikrotik RouterBoard 433AH have PCI slot 18 wired to INT0 on the PCI Bus.
This is different from e.g. Atheros PB42 and Ubiquiti boards.
* Check for hint hint.pcib.0.baseslot=X, where X is number of base slot;
* If hint not supplied print a warning and use default AR71XX_PCI_BASE_SLOT;
PR: kern/174978
Approved by: adrian (mentor)
are written out.
This allows EEPROM-less NICs on the AR7241 PCIe bus to be correctly
initialised.
Tested:
* AP91 (AR7240+AR9285) - the existing board support didn't break;
* AP99 (AR7241+AR9287) - this fixed the configuration of the AR9287 PCI.
This seems to break at least my test board here (AR71xx + AR8316 switch
PHY). Since I do have a whole sleuth of "normal" PHY boards (with
an AR71xx on a normal PHY port), I'll do some further testing with those
to determine whether this is a general issue, or whether it's limited
to the behaviour of the "fake" dedicated PHY port mode on these atheros
switches.
