Commit Graph

61 Commits

Author SHA1 Message Date
Marcel Moolenaar
23fbc06bfc Support lbc interrupts:
o   Save and clear the LTESR register in the interrupt handler.
o   In lbc_read_reg(), return the saved LTESR register value if applicable
    (i.e. when the saved value is not invalid (read: ~0U)).
o   In lbc_write_reg(), clear the bits in the saved register when when it's
    written to and when the asved value is not invalid.
o   Also in lbc_write_reg(), the LTESR register is unlocked (in H/W) when
    bit 1 of LTEATR is cleared. We use this to invalidate our saved LTESR
    register value. Subsequent reads and write go to H/W directly.

While here:
o   In lbc_read_reg() & lbc_write_reg(), add some belts and suspenders to
    catch when register offsets are out of range.
o   In lbc_attach(), initialize completely and don't leave something left
    for lbc_banks_enable().
2012-07-03 00:06:14 +00:00
Marcel Moolenaar
8609d8293d Properly implement the bus_config_intr, bus_setup_intr and bus_teardown_intr
methods so that MI drvers can depend on us doing the right thing instead
of having to go around us and call MD code directly. See the FDT code for
example (not for long though).
2012-07-02 23:41:56 +00:00
Rafal Jaworowski
53a123e516 Import eSDHC driver for Freescale integrated controller.
Obtained from:	Freescale, Semihalf
Written by:	Michal Dubiel
2012-05-26 21:07:15 +00:00
Rafal Jaworowski
0a67fa33d6 Move OpenPIC FDT bus glue to a shared location, so that other PowerPC
platforms can use it, not only MPC85XX.

This is just reorg, no functional changes.
2012-05-26 21:02:49 +00:00
Marcel Moolenaar
f6703dd295 A few improvements:
1.  Define all registers. These definitions are needed to support
    the FCM driver for direct-connect NAND.
2.  Repurpose lbc_read_reg() and lbc_write_reg() for use by localbus
    attached device drivers. Use bus_space functions directly in the
    lbc driver itself.
3.  Be smarter about programming LAWs and mapping memory. The ranges
    defined in the FDT are per bank (= chip select) and since we can
    have up to 8 banks, we could easily use more than 8 LAWs or TLB
    enrties when per-bank memory ranges need multiple LAWs or TLBs
    due to alignment or size constraints.
    We now combine all memory ranges into the fewest possible set of
    contiguous regions and program the hardware for that. Thus, a
    cleverly written FDT with 8 devices may still only need 1 LAW or
    1 TLB entry. Note that the memory ranges can be assigned randomly
    to the banks. We sort as we build to handle that.
4.  Support the FCM when programming the OR register. This is mostly
    for documention purposes as we do not have a way to define the
    mode for a bank.
5.  Remove Semihalf-ism: do not define DEBUG (only to undefine it
    again).
2012-05-24 21:23:13 +00:00
Marcel Moolenaar
5704576a0a Remove Semihakf-ism. DEBUG is a kernel configuration option. It
should not be defined in source files.
2012-05-24 21:09:38 +00:00
Marcel Moolenaar
e845939dc1 Just return if the size of the window is 0. This can happen when the
FDT does not define all ranges possible for a particular node (e.g.
PCI).
While here, only update the trgt_mem and trgt_io pointers if there's
no error. This avoids that we knowingly write an invalid target (= -1).
2012-05-24 21:07:10 +00:00
Marcel Moolenaar
05917fee1b Either the I/O port range or the memory mapped I/O range may not be
defined in the FDT. The range will have a zero size in that case.
2012-05-24 21:01:35 +00:00
Nathan Whitehorn
2a134f71d1 Fix missing header for powerpc_iomb().
Pointy hat to:	me
2012-04-23 15:47:07 +00:00
Nathan Whitehorn
13d47f302f Replace eieio; sync for creating bus-space memory barriers with sync.
sync performs a strict superset of the functions of eieio, so using both
is redundant. While here, expand bus barriers to all bus_space operations,
since many drivers do not correctly use bus_space_barrier().

In principle, we can also replace sync just with eieio, for a significant
performance increase, but it remains to be seen whether any poorly-written
drivers currently depend on the side effects of sync to properly function.

MFC after:	1 week
2012-04-22 18:54:51 +00:00
Marius Strobl
4b7ec27007 - There's no need to overwrite the default device method with the default
one. Interestingly, these are actually the default for quite some time
  (bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9)
  since r52045) but even recently added device drivers do this unnecessarily.
  Discussed with: jhb, marcel
- While at it, use DEVMETHOD_END.
  Discussed with: jhb
- Also while at it, use __FBSDID.
2011-11-22 21:28:20 +00:00
Marcel Moolenaar
f1a8a35846 Fix r222813: we need to include sys/cpuset.h. because the PIC interface
uses cpuset_t. While here, fix the redundant inclusion of sys/bus.h and
order the includes.

Approved by:	re (blanket)
2011-07-31 18:30:38 +00:00
Attilio Rao
c7df91af4b MFC 2011-05-29 00:59:38 +00:00
Marcel Moolenaar
8a4b7c64b3 o Determine the number of LAWs in a way the is future proof. Only the
MPC8555(E) has 8 LAWs, so don't make that the default case. Current
    processors have 12 LAWs so use that as the default instead.
o   Determine the target ID of the PCI/PCI-X and PCI-E controllers in
    a way that's more future proof. There's almost a perfect mapping
    from HC register offset to target ID, so use that as the default.
    Handle the MPC8548(E) specially, since it has a non-standard target
    ID for the PCI-E controller. Don't worry about whether the processor
    implements the target ID here, because we should not get called for
    PCI/PCI-X or PCI-E host controllers that don't exist.
2011-05-28 19:14:16 +00:00
Marcel Moolenaar
7591d5a373 Remove unused defines. They're distracting... 2011-05-28 16:30:24 +00:00
Attilio Rao
a713c4a5c3 Fix compilation.
Submitted by:	andreast
2011-05-18 19:46:26 +00:00
John Baldwin
f9a9473702 Retire isa_setup_intr() and isa_teardown_intr() and use the generic bus
versions instead.  They were never needed as bus_generic_intr() and
bus_teardown_intr() had been changed to pass the original child device up
in 42734, but the ISA bus was not converted to new-bus until 45720.
2011-05-06 13:48:53 +00:00
Marcel Moolenaar
607ebaaf0c Rename INTR_VEC to MAP_IRQ. From the OFW or FDT we obtain a
PIC handle with interrupt pin. This we map to the resource
called SYS_RES_IRQ.
2011-02-02 05:58:51 +00:00
Marcel Moolenaar
6d2d7b8c0d Fix the interrupt code, broken 7 months ago. The interrupt framework
already supported nested PICs, but was limited to having a nested
AT-PIC only. With G5 support the need for nested OpenPIC controllers
needed to be added. This was done the wrong way and broke the MPC8555
eval system in the process.

OFW, as well as FDT, describe the interrupt routing in terms of a
controller and an interrupt pin on it. This needs to be mapped to a
flat and global resource: the IRQ. The IRQ is the same as the PCI
intline and as such needs to be representable in 8 bits. Secondly,
ISA support pretty much dictates that IRQ 0-15 should be reserved
for ISA interrupts, because of the internal workins of south bridges.
Both were broken.

This change reverts revision 209298 for a big part and re-implements
it simpler. In particular:
o   The id() method of the PIC I/F is removed again. It's not needed.
o   The openpic_attach() function has been changed to take the OFW
    or FDT phandle of the controller as a second argument. All bus
    attachments that previously used openpic_attach() as the attach
    method of the device I/F now implement as bus-specific method
    and pass the phandle_t to the renamed openpic_attach().
o   Change powerpc_register_pic() to take a few more arguments. In
    particular:
    -   Pass the number of IPIs specificly. The number of IRQs carved
	out for a PIC is the sum of the number of int. pins and IPIs.
    -   Pass a flag indicating whether the PIC is an AT-PIC or not.
	This tells the interrupt framework whether to assign IRQ 0-15
	or some other range.
o   Until we implement proper multi-pass bus enumeration, we have to
    handle the case where we need to map from PIC+pin to IRQ *before*
    the PIC gets registered. This is done in a similar way as before,
    but rather than carving out 256 IRQs per PIC, we carve out 128
    IRQs (124 pins + 4 IPIs). This is supposed to handle the G5 case,
    but should really be fixed properly using multiple passes.
o   Have the interrupt framework set root_pic in most cases and not
    put that burden in PIC drivers (for the most part).
o   Remove powerpc_ign_lookup() and replace it with powerpc_get_irq().
    Remove IGN_SHIFT, INTR_INTLINE and INTR_IGN.

Related to the above, fix the Freescale PCI controller driver, broken
by the FDT code. Besides not attaching properly, bus numbers were
assigned improperly and enumeration was broken in general. This
prevented the AT PIC from being discovered and interrupt routing to
work properly. Consequently, the ata(4) controller stopped functioning.

Fix the driver, and FDT PCI support, enough to get the MPC8555CDS
going again. The FDT PCI code needs a whole lot more work.

No breakages are expected, but lackiong G5 hardware, it's possible
that there are unpleasant side-effects. At least MPC85xx support is
back to where it was 7 months ago -- it's amazing how badly support
can be broken in just 7 months...

Sponsored by: Juniper Networks
2011-01-29 20:58:38 +00:00
Marcel Moolenaar
696703e5ea Have nexus behave the same as the one on ARM (marvell SoCs), so as to
prevent warnings during boot WRT to the fdtbus attachment.
2011-01-29 20:28:17 +00:00
Nathan Whitehorn
b2a237be5c Restructure how reset and poweroff are handled on PowerPC systems, since
the existing code was very platform specific, and broken for SMP systems
trying to reboot from KDB.

- Add a new PLATFORM_RESET() method to the platform KOBJ interface, and
  migrate existing reset functions into platform modules.
- Modify the OF_reboot() routine to submit the request by hand to avoid
  the IPIs involved in the regular openfirmware() routine. This fixes
  reboot from KDB on SMP machines.
- Move non-KDB reset and poweroff functions on the Powermac platform
  into the relevant power control drivers (cuda, pmu, smu), instead of
  using them through the Open Firmware backdoor.
- Rename platform_chrp to platform_powermac since it has become
  increasingly Powermac specific. When we gain support for IBM systems,
  we will grow a new platform_chrp.
2010-08-31 15:27:46 +00:00
Rafal Jaworowski
d1d3233ebd Convert Freescale PowerPC platforms to FDT convention.
The following systems are affected:

  - MPC8555CDS
  - MPC8572DS

This overhaul covers the following major changes:

  - All integrated peripherals drivers for Freescale MPC85XX SoC, which are
    currently in the FreeBSD source tree are reworked and adjusted so they
    derive config data out of the device tree blob (instead of hard coded /
    tabelarized values).

  - This includes: LBC, PCI / PCI-Express, I2C, DS1553, OpenPIC, TSEC, SEC,
    QUICC, UART, CFI.

  - Thanks to the common FDT infrastrucutre (fdtbus, simplebus) we retire
    ocpbus(4) driver, which was based on hard-coded config data.

Note that world for these platforms has to be built WITH_FDT.

Reviewed by:	imp
Sponsored by:	The FreeBSD Foundation
2010-07-11 21:08:29 +00:00
Nathan Whitehorn
0870f0be13 Move the EOI logic when starting ithreads into intr_machdep instead of
relying on it as a side effect of PIC_MASK() in the PIC drivers, and add
an inmplementation of assign_cpu() for the kernel interrupt layer.
2010-07-06 15:27:05 +00:00
Marcel Moolenaar
8a35d194f2 Remove the unneeded header <machine/intr.h>. 2010-07-02 02:17:39 +00:00
Marcel Moolenaar
bcec9ed0f1 Assign PCI intline values for ISA interrupts using the new INTR_VEC()
macro.
2010-06-24 05:49:58 +00:00
Marcel Moolenaar
ec120b9476 Pass the device_t of the AT PIC driver to atpic_intr() so that
we don't have to use a global variable. Pass a NULL frame pointer
to the dispatch function just like openpic(4).
2010-06-24 05:05:18 +00:00
Marcel Moolenaar
79312a0b25 With openpic(4) using active-low as the default polarity, reconfigure
the internal interrupt sources as active-high. The internal interrupt
sources are disabled when programmed as active-low.

Note that the internal interrupts have no sense bit like the external
interrupts. We program them as edge-triggered to make sure we write a
0 value to a reserved register. It does not in any way say anything
about the sense of internal interrupt.
2010-06-23 23:16:27 +00:00
Nathan Whitehorn
08393b3efa Configure interrupts on SMP systems to be distributed among all online
CPUs by default, and provide a functional version of BUS_BIND_INTR().
While here, fix some potential concurrency problems in the interrupt
handling code.
2010-06-23 22:33:03 +00:00
Nathan Whitehorn
eaef5f0af8 Provide for multiple, cascaded PICs on PowerPC systems, and extend the
OFW interrupt map interface to also return the device's interrupt parent.

MFC after:	8.1-RELEASE
2010-06-18 14:06:27 +00:00
Marcel Moolenaar
b41169fdce Fix an off-by-one bug for the number of slots on a PCI/PCI-X bus.
We failed to setup PCI devices on slot 31 and that's where the
SATA controller is for the P2020 eval board.
2010-03-23 23:46:28 +00:00
Marcel Moolenaar
e4ee16b41e Add definitions for a 4th PCI host controller. No Freescale processor
has all 4 implemented, but across the processors we now support all the
combinations. For example, the MPC8533 doesn't have a PCI controller
at 0xA0000, but does at 0xB0000.
2010-03-23 20:12:53 +00:00
Marcel Moolenaar
7432531341 Make PCI Express host controllers functional, by:
1.  checking whether there's a link before initializing devices
    on the bus. When there's no link any access onto the bus
    will wedge the CPU.
2.  synthesizing the class & subclass so that the host controller
    appears as a standard PCI bridge, rather than a PowerPC CPU.
2010-02-01 17:51:01 +00:00
Marcel Moolenaar
f0f77f7219 Use the capability pointer to indicate whether the host controller is
PCI Express, rather than a bit-field (boolean). Saving the capability
pointer this way makes access to capability-specific configuration
registers easy and efficient.
2010-02-01 17:26:58 +00:00
Marcel Moolenaar
8429f8e8f4 Don't check the device ID. Instead, check the class, subclass and
programming I/F. New SoC designs have different device IDs, but
don't need special treatment. Consequently, we fail to probe and
attach for no other reason than not having added the device ID to
the code.

Bank on Freescale's sense of backward compatibility and assume
that if we find a host controller, we know how work with it.

This fixes detection of the PCI Express host controllers on
Freescale's QorIQ family of processors (P1, P2 and P4).
2010-01-29 20:37:12 +00:00
Marcel Moolenaar
0c8e3b18f0 Always allocate PCI/ISA interrupts as shareable so that shared
interrupts don't cause driver attach failures.
2009-11-20 17:59:50 +00:00
Rafal Jaworowski
570255d8a5 Do not use OCP85XX_LBC_OFF twice when accessing LBC registers on MPC85XX.
It turns LBC control registers were not programmed correctly on MPC85XX. We
were accessing bogus addresses as the base offset (OCP85XX_LBC_OFF) was
erroneously added during offset calculations.  Effectively the state of LBC
control registers was not altered by the kernel initialization code, but
everything worked as long as we coincided to use the same settings (LBC decode
windows) as firmware has initialized.

Submitted by:	Lukasz Wojcik
Reviewed by:	marcel
Approved by:	re (kensmith)
Obtained from:	Semihalf
2009-07-21 08:38:45 +00:00
Rafal Jaworowski
b53ce17515 More precise description of the DS1553 driver.
Pointed out by:	stas
2009-06-24 15:48:20 +00:00
Rafal Jaworowski
f07ef6e4e3 DS1553 RTC module driver. On the MPC8555CDS system it hangs off of the LBC bus.
Obtained from:	Semihalf
2009-06-22 15:48:47 +00:00
Rafal Jaworowski
757cb6dbdf Integrated I2C controller driver (found in MPC85xx and other SOC parts).
Obtained from:	Freescale, Semihalf
2009-06-22 15:34:32 +00:00
Rafal Jaworowski
02b553cafc Initial version of the sec(4) driver for the integrated security engine found
in Freescale system-on-chip devices.

The following algorithms and schemes are currently supported:
  - 3DES, AES, DES
  - MD5, SHA1, SHA256, SHA384, SHA512

Reviewed by:	philip
Obtained from:	Freescale, Semihalf
2009-06-06 09:37:55 +00:00
Marcel Moolenaar
591dea8c59 Mark the cascaded AT interrupt handler as MP safe to avoid having
it grab Giant. The next step would be to make it a filter.
2009-05-31 01:56:06 +00:00
Rafal Jaworowski
28bb01e5ba Initial support for SMP on PowerPC MPC85xx.
Tested with Freescale dual-core MPC8572DS development system.

Obtained from:	Freescale, Semihalf
2009-05-21 11:43:37 +00:00
Rafal Jaworowski
2a476ed9ed Skip interleaved RAM target on MPC85xx during renitialization of the local
access windows. This eliminates hangs on systems which are configured to use
interleaved mode: prior to this fix we were simply cutting ourselves from
access to the main memory in this case.

Obtained from:	Freescale, Semihalf
2009-05-21 11:37:56 +00:00
Marcel Moolenaar
ac741ae511 Add suppport for ISA and ISA interrupts to make the ATA
controller in the VIA southbridge functional in the CDS
(Configurable Development System) for MPC85XX.
The embedded USB controllers look operational but the
interrupt steering is still wrong.
2009-04-24 03:51:11 +00:00
Rafal Jaworowski
389e4721e9 Make MPC85xx LAW handling and reset routines aware of the MPC8548 variant.
Inspired by discussion with Alexey V Fedorov on freebsd-powerpc@.
2009-03-13 06:28:20 +00:00
Rafal Jaworowski
25c22eb425 Extend and improve MPC85XX Local Bus management.
- Make LBC resources management self-contained: introduce explicit LBC
  resources definition (much like the OCP), provide dedicated rman for LB mem
  space.

- Full configuration of an LB chip select device: program LAW and BR/OR, map
  into KVA, handle all LB attributes (bus width, machine select, ecc,
  write protect etc).

- Factor out LAW manipulation routines into shared code, adjust OCP area
  accordingly.

- Other LBC fixes and clean-ups.

Obtained from:	Semihalf
2008-12-18 18:27:12 +00:00
Rafal Jaworowski
51d059c6de Minor clean up of BookE/MPC85XX: iprove naming and style(9). 2008-12-17 15:31:15 +00:00
Rafal Jaworowski
fe48da3f41 Improve MPC85XX helper routines.
- Move CCSR accessors to the shared MPC85XX area
- Simplify SVR version subfield handling
- Adjust OCP
2008-12-17 15:27:49 +00:00
Marcel Moolenaar
08077f589c Add a driver for the Local Bus Controller.
Obtained from:	Juniper Networks, Inc.
2008-10-25 06:03:40 +00:00
Marcel Moolenaar
bd616bc87e Assign 0xff800000-0xffffffff to the LBC controller. That's where
the NOR flash lives by default.
2008-10-25 05:57:36 +00:00