Commit Graph

257330 Commits

Author SHA1 Message Date
markj
2a30688b57 Assume that pmap_l1() will return a PTE.
pmaps on RISC-V always have an L1 page table page, so we don't need to
check for this when performing lookups.

Reviewed by:	jhb
MFC after:	1 week
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D18563
2018-12-14 21:03:01 +00:00
markj
96ce579a00 Add a QEMU config for RISC-V.
Reviewed by:	jhb
MFC after:	1 week
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D18560
2018-12-14 21:00:41 +00:00
markj
fa544b2f75 Enable witness(4) in the RISC-V GENERIC config.
Reviewed by:	jhb
MFC after:	1 week
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D18559
2018-12-14 20:57:57 +00:00
imp
d414fafdca atomic_cmpset return value is also an int. 2018-12-14 19:48:42 +00:00
imp
528cf023e0 atomic_fcmpset* return int, not the type of *.
fcmpset returns true/false as a int, so make the return types and
variables match the int to be consistent with other arch.

Reviewed by: cognet@
Differential Revision: https://reviews.freebsd.org/D18557
2018-12-14 19:14:51 +00:00
markj
f2faa35438 Clean up the riscv pmap_bootstrap() implementation.
- Build up phys_avail[] in a single loop, excluding memory used by
  the loaded kernel.
- Fix an array indexing bug in the aforementioned phys_avail[]
  initialization.[1]
- Remove some unneeded code copied from the arm64 implementation.

PR:		231515 [1]
Reviewed by:	jhb
MFC after:	2 weeks
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D18464
2018-12-14 18:50:32 +00:00
manu
4cc6000919 allwinner: aw_pwm: Read value at attach
The booloaded might have configured the pwm controller so read the values.
2018-12-14 18:39:17 +00:00
manu
5088b48b10 pwm(8): Add percentage value support for duty cycle 2018-12-14 18:38:10 +00:00
manu
7e40e33031 pwm: Convert period and duty to unsigned int
We don't need a 64 bits value to store nanoseconds

Discused with:	ian, jhibbits
2018-12-14 18:37:26 +00:00
markj
742b58778c Add support for the nForce MCP89 adapter.
PR:		234015
Submitted by:	Andrejs Bogdanovs <sinchiroca86@gmail.com>
MFC after:	1 week
2018-12-14 18:16:35 +00:00
mw
696d820352 Fix TPM driver compilation from r342084
Include recent ACPI_ID_PROBE API change.
2018-12-14 17:43:35 +00:00
mw
9b71ef63cd Introduce driver for TPM 2.0 in CRB and FIFO (TIS) modes
It was written basing on:
TCG PC Client Platform TPM Profile (PTP) Specification Version 22, Revision 1.03.
It only supports Locality 0. Interrupts are only supported in FIFO mode.

The driver in FIFO mode was tested on x86 with Infineon SLB9665 discrete TPM chip.
Driver in both modes was also tested on qemu with swtpm running on host.

Submitted by: Kornel Duleba <mindal@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Differential Revision: https://reviews.freebsd.org/D18048
2018-12-14 16:14:36 +00:00
kadesai
c0c0f0acbf Compilation failure on ppc and mips due to Revision 342066.
Adding extra memset on chain frame.

Submitted by: Sumit Saxena <sumit.saxena@broadcom.com>
Reviewed by:  Kashyap Desai <Kashyap.Desai@broadcom.com>
Approved by:  ken
MFC after:  3 days
Sponsored by:   Broadcom Inc
2018-12-14 10:49:48 +00:00
manu
3b03c9e70f arm64: allwinner: axp81x: Fix double invertion for FLDO1
This fix booting on A64 boards when disabling the unused regulators at boot.
We did disable all the regulator handled by register 0x13 which of course contain
mandatory regulators for the board to be up.

Reported by:	Mark Millard <marklmi@yahoo.com>
X-MFC-With:	r340848
2018-12-14 10:26:17 +00:00
avg
5b7e69bb0f ichwd: add Sunrise Point-LP ID
Submitted by:	Tetsuya Uemura <t_uemura@macome.co.jp>
Tested by:	Tetsuya Uemura <t_uemura@macome.co.jp>
MFC after:	2 weeks
Relnotes:	maybe
2018-12-14 09:30:43 +00:00
avg
a454a47086 ichwd: add support for clearing No Reboot bit in TCOv4
This is based on a patch developed by
Tetsuya Uemura <t_uemura@macome.co.jp>.
Many thanks!

Submitted by:	Tetsuya Uemura <t_uemura@macome.co.jp> (earlier version)
Tested by:	Tetsuya Uemura <t_uemura@macome.co.jp>
MFC after:	2 weeks
2018-12-14 09:28:20 +00:00
eugen
153edbc0ab ng_bpf.4: fix EXAMPLES: do not activate promiscuous mode
PR:		102719
MFC after:	3 days
2018-12-14 09:24:14 +00:00
kadesai
229ef35384 Driver version upgrade 07.708.02.00-fbsd
Submitted by: Sumit Saxena <sumit.saxena@broadcom.com>
Reviewed by:  Kashyap Desai <Kashyap.Desai@broadcom.com>
Approved by:  ken
MFC after:  3 days
Sponsored by:   Broadcom Inc
2018-12-14 08:06:39 +00:00
kadesai
834a7a817e This patch will increase debug level as current logging level has
very minimal prints and even few important messages will not get logged.

Submitted by: Sumit Saxena <sumit.saxena@broadcom.com>
Reviewed by:  Kashyap Desai <Kashyap.Desai@broadcom.com>
Approved by:  ken
MFC after:  3 days
Sponsored by:   Broadcom Inc
2018-12-14 08:05:49 +00:00
kadesai
20341fba62 Change IOC INIT wait time to 180 secs to keep it inline with timeout
used by internal DCMDs.

Submitted by: Sumit Saxena <sumit.saxena@broadcom.com>
Reviewed by:  Kashyap Desai <Kashyap.Desai@broadcom.com>
Approved by:  ken
MFC after:  3 days
Sponsored by:   Broadcom Inc
2018-12-14 08:05:01 +00:00
kadesai
e61876e4a9 This patch will add support for NVME PRPs creation by driver for fastpath
capable IOs. NVME specification supports specific type of scatter gather list
called as PRP (Physical Region Page) for IO data buffers. Since NVME drive is
connected behind SAS3.5 tri-mode adapter, MegaRAID driver/firmware has to convert
OS SGLs in native NVMe PRP format. For IOs sent to firmware, MegaRAID firmware
does this job of OS SGLs to PRP translation and send PRPs to backend NVME device.
For fastpath IOs, driver will do this OS SGLs to PRP translation.

Submitted by: Sumit Saxena <sumit.saxena@broadcom.com>
Reviewed by:  Kashyap Desai <Kashyap.Desai@broadcom.com>
Approved by:  ken
MFC after:  3 days
Sponsored by:   Broadcom Inc
2018-12-14 08:04:16 +00:00
kadesai
dc69dfc3bf This patch will add support for new DCMD to get PD information and a single data structure
to specify LD and JBOD.

Submitted by: Sumit Saxena <sumit.saxena@broadcom.com>
Reviewed by:  Kashyap Desai <Kashyap.Desai@broadcom.com>
Approved by:  ken
MFC after:  3 days
Sponsored by:   Broadcom Inc
2018-12-14 08:03:28 +00:00
kadesai
514f953e0e To improve RAID 1/10 Write performance, OS drivers need to issue the
required Write IOs as Fast Path IOs (after the appropriate checks
allowing Fast Path to be used) to the appropriate physical drives
(translated from the OS logical IO) and wait for all Write IOs to complete.

Design: A write IO on RAID volume will be examined if it can be sent in
Fast Path based on IO size and starting LBA and ending LBA falling on to
a Physical Drive boundary. If the underlying RAID volume is a RAID 1/10,
driver issues two fast path write IOs one for each corresponding physical
drive after computing the corresponding start LBA for each physical drive.
Both write IOs will have the same payload and are posted to HW such that
replies land in the same reply queue.

If there are no resources available for sending two IOs, driver will send
the original IO from upper layer to RAID volume through the Firmware.

When both IOs are completed by HW, the resources will be released
and SCSI IO completion handler will be called.

Submitted by: Sumit Saxena <sumit.saxena@broadcom.com>
Reviewed by:  Kashyap Desai <Kashyap.Desai@broadcom.com>
Approved by:  ken
MFC after:  3 days
Sponsored by:   Broadcom Inc
2018-12-14 08:02:44 +00:00
kadesai
8384082de5 Detect sequential Write IOs and pass the hint that it is part of sequential
stream to help HBA Firmware do the Full Stripe Writes. For read IOs on
certain RAID volumes like Read Ahead volumes,this will help driver to
send it to Firmware even if the IOs can potentially be sent to
hardware directly (called fast path) bypassing firmware.

Design: 8 streams are maintained per RAID volume as per the combined
firmware/driver design. When there is no stream detected the LRU stream
is used for next potential stream and LRU/MRU map is updated to make this
as MRU stream. Every time a stream is detected the MRU map
is updated to make the current stream as MRU stream.

Submitted by: Sumit Saxena <sumit.saxena@broadcom.com>
Reviewed by:  Kashyap Desai <Kashyap.Desai@broadcom.com>
Approved by:  ken
MFC after:  3 days
Sponsored by:   Broadcom Inc
2018-12-14 08:01:49 +00:00
kadesai
f3d059705f This patch will add new interface to support more than 256 JBODs.
Submitted by: Sumit Saxena <sumit.saxena@broadcom.com>
Reviewed by:  Kashyap Desai <Kashyap.Desai@broadcom.com>
Approved by:  ken
MFC after:  3 days
Sponsored by:   Broadcom Inc
2018-12-14 08:00:45 +00:00
kadesai
bdabc799dc This patch will add support for divert bitmap in RAID map. Divert bitmap is supported for
SAS3.5 adapters only.

Submitted by: Sumit Saxena <sumit.saxena@broadcom.com>
Reviewed by:  Kashyap Desai <Kashyap.Desai@broadcom.com>
Approved by:  ken
MFC after:  3 days
Sponsored by:   Broadcom Inc
2018-12-14 08:00:01 +00:00
kadesai
51eed342e9 This patch will add support for new Dynamic RaidMap to have different sizes
for different number of supported VDs for SAS3.5 MegaRAID adapters.

Submitted by: Sumit Saxena <sumit.saxena@broadcom.com>
Reviewed by:  Kashyap Desai <Kashyap.Desai@broadcom.com>
Approved by:  ken
MFC after:  3 days
Sponsored by:   Broadcom Inc
2018-12-14 07:59:09 +00:00
kadesai
3d8e3cc029 This patch will add support for next generation(SAS3.5) of Tri mode(SAS, SATA, NVMe)
MegaRAID adapters.

Submitted by: Sumit Saxena <sumit.saxena@broadcom.com>
Reviewed by:  Kashyap Desai <Kashyap.Desai@broadcom.com>
Approved by:  ken
MFC after:  3 days
Sponsored by:   Broadcom Inc
2018-12-14 07:57:00 +00:00
mjg
8598ea893e vfs: mostly depessimize NDINIT_ALL
1) filecaps_init was unnecesarily a function call
2) an asignment at the end was preventing tail calling of cap_rights_init

Sponsored by:	The FreeBSD Foundation
2018-12-14 03:55:08 +00:00
jkim
ded45cae09 Do not complain when /dev/crypto does not exist.
Now the new devcrypto engine is enabled since r342009, many users started
seeing "Could not open /dev/crypto: No such file or directory".  Disable
the annoying error message as it is not very useful anyway.

Note the patch was submitted upstream.

https://github.com/openssl/openssl/pull/7896
2018-12-14 01:06:34 +00:00
jkim
b72e59ab7d MFV: r342049
Merge ACPICA 20181213.
2018-12-14 00:40:38 +00:00
bcran
ad1e51c81c Cast error message in efi_main.c to CHAR16* to avoid build error 2018-12-13 23:49:20 +00:00
bcran
887cca5fe5 Print an error message in efi_main.c if we can't allocate memory for the heap
With the default Qemu parameters, only 128MB RAM gets given to a VM. This causes
the loader to be unable to allocate the 64MB it needs for the heap. This change
makes the cause of the error more obvious.

Differential Revision:	https://reviews.freebsd.org/D17958
2018-12-13 23:20:58 +00:00
mjg
a2507cdb8a dtrace: fix userspace access on boxes with SMAP
dtrace has its own routines which were not updated after SMAP support got
implemented. Use ifunc just like for other routines.

This in particular fixes ustack().

Reviewed by:	markj
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D18542
2018-12-13 20:09:38 +00:00
chuck
2fd83c3710 nda(4) fix check for Dataset Management support
In the nda(4) driver, only set DISKFLAG_CANDELETE (a.k.a. can support
BIO_DELETE) if the drive supports Dataset Management. There are reports
that without this check, VMWare Workstation does not work reliably.

Fix is to check the ONCS field in the NVMe Controller Data structure for
support. This check previously existed but did not survive the
big-endian changes.

Reported by: yuripv@yuripv.net
Reviewed by: imp, mav, jimharris
Approved by: imp (mentor)
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D18493
2018-12-13 13:25:37 +00:00
des
e38d227e8d Create /etc/authpf, used by authpf(8) and authpf-noip(8).
MFC after:	1 week
2018-12-13 12:58:42 +00:00
mm
426936ff22 MFV r341771,342040,342041:
Sync libarchive with vendor.

Relevant vendor changes:
  PR #1102: RAR5 reader - fix big-endian problems
  PR #1105: Fix various crash, memory corruption and infinite loop conditions
  PR #1107: RAR5 reader: removed an unused function: bf_is_last_block

MFC after:	1 week
2018-12-13 11:18:45 +00:00
ae
b3a32fc226 Plug memory leak for AES_*_NIST_GMAC algorithms.
swcr_newsession() allocates sw_ictx for these algorithms, thus we need
to free() it in swcr_freesession().

PR:		233907
MFC after:	1 week
2018-12-13 08:59:51 +00:00
dim
c44acdff64 Fix dates that I set into the future incorrectly.
Noticed by:		ler
2018-12-13 06:59:55 +00:00
jhibbits
9df2142898 powerpc/booke: Change KERNBASE to be physical load address
Previous commits have made VM_MIN_KERNEL_ADDRESS its own separate entity,
and rebased the kernel around that address instead of KERNBASE.  This commit
pulls the trigger to rebase KERNBASE to a physical load address.  The
eventual goal is to align the address with the AIM KERNBASE, but at this
time that's not an option.

Currently a Book-E kernel must be loaded on a 64MB boundary, due to size
issues.  The common load address is at the 64MB mark (0x04000000), so simply
make that the default KERNBASE.

As of this commit, Book-E kernels can be loaded and booted with ubldr.

MFC after:	3 weeks
2018-12-13 05:07:39 +00:00
jhibbits
b7802808dc powerpcspe: Fix GPR handling in SPE exception handler
Optimize the exception handler to only save and load the upper word of the
GPRs used in the emulating instruction.  This reduces the save/load
overhead, and as a side effect does not overwrite the upper word of any
temporary register.

With this commit I am now able to run editors/abiword and math/gnumeric on a
e500-based system.

MFC after:	1 week
MFC With:	r341752,r341751
2018-12-13 04:48:28 +00:00
mmacy
6bf6ad0f09 Generalize AES iov optimization
Right now, aesni_cipher_alloc does a bit of special-casing
for CRYPTO_F_IOV, to not do any allocation if the first uio
is large enough for the requested size. While working on ZFS
crypto port, I ran into horrible performance because the code
uses scatter-gather, and many of the times the data to encrypt
was in the second entry. This code looks through the list, and
tries to see if there is a single uio that can contain the
requested data, and, if so, uses that.

This has a slight impact on the current consumers, in that the
check is a little more complicated for the ones that use
CRYPTO_F_IOV -- but none of them meet the criteria for testing
more than one.

Submitted by:	sef at ixsystems.com
Reviewed by:	cem@
MFC after:	3 days
Sponsored by:	iX Systems
Differential Revision:	https://reviews.freebsd.org/D18522
2018-12-13 04:40:53 +00:00
imp
ea93db4e32 Correctly implemenet atomic_swap_long for mips64.
MIPS64 has 64-bit longs, so use uint64_t for it, otherwise uint32_t.
sizeof(long) == sizeof(ptr) for all platforms, so define
atomic_swap_ptr in terms of atomic_swap_long.

Submitted by: hps@
2018-12-13 00:42:26 +00:00
manu
a3af78d3ad mv_thermal: Add thermal driver for AP806 and CP110 thermal sensor
Sponsored by:	Rubicon Communications, LLC ("Netgate")
2018-12-12 22:33:05 +00:00
manu
7feac2f7e8 arm64: mv_cp110_icu: Fix build 2018-12-12 22:24:30 +00:00
manu
cce48d98de mv_gpio: Since it's also an interrupt controller, attach sooner
Sponsored by:	Rubicon Communications, LLC ("Netgate")
2018-12-12 22:10:11 +00:00
manu
e22b714d0f sdhci_xenon: Add Marvell 8k compatible string
Sponsored by:	Rubicon Communications, LLC ("Netgate")
2018-12-12 22:09:35 +00:00
manu
46170dc3e9 arm64: Add mv_cp110_icu and mv_cp110_gicp
icu is a interrupt concentrator in the CP110 block and gicp
is a gic extension to allow interrupts in the CP block to be turned
into GIC SPI interrupts

Sponsored by:	Rubicon Communications, LLC ("Netgate")
2018-12-12 22:08:43 +00:00
manu
35ad6ef573 twsi: Clean up marvell part and add support for Marvell 7k/8k
Sponsored by:	Rubicon Communications, LLC ("Netgate")
2018-12-12 22:05:07 +00:00
manu
6c963cc241 arm64: marvell: Add cp110 clock controller support
The cp110 clock controller controls the clocks and gate of the CP110
hardware block.

Every clock/gate are implemented except the NAND clock.

Sponsored by:	Rubicon Communications, LLC ("Netgate")
2018-12-12 22:04:21 +00:00