Commit Graph

159 Commits

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27723bd87e Adding hardware ID for RTL810x PCIe found on HP Pavilion DV2-1022AX.
Reviewed by:	yongari
Approved by:	re (kib, kensmith)
2009-07-14 04:35:13 +00:00
rwatson
be5740a255 Use if_maddr_rlock()/if_maddr_runlock() rather than IF_ADDR_LOCK()/
IF_ADDR_UNLOCK() across network device drivers when accessing the
per-interface multicast address list, if_multiaddrs.  This will
allow us to change the locking strategy without affecting our driver
programming interface or binary interface.

For two wireless drivers, remove unnecessary locking, since they
don't actually access the multicast address list.

Approved by:	re (kib)
MFC after:	6 weeks
2009-06-26 11:45:06 +00:00
attilio
b523608331 When user_frac in the polling subsystem is low it is going to busy the
CPU for too long period than necessary.  Additively, interfaces are kept
polled (in the tick) even if no more packets are available.
In order to avoid such situations a new generic mechanism can be
implemented in proactive way, keeping track of the time spent on any
packet and fragmenting the time for any tick, stopping the processing
as soon as possible.

In order to implement such mechanism, the polling handler needs to
change, returning the number of packets processed.
While the intended logic is not part of this patch, the polling KPI is
broken by this commit, adding an int return value and the new flag
IFCAP_POLLING_NOCOUNT (which will signal that the return value is
meaningless for the installed handler and checking should be skipped).

Bump __FreeBSD_version in order to signal such situation.

Reviewed by:	emaste
Sponsored by:	Sandvine Incorporated
2009-05-30 15:14:44 +00:00
yongari
77dde87e61 For RTL8139C+ controllers, have controller handle padding short
checksum offload frames. Software workaround used for broken
controllers(RTL8169, RTL8168, RTL8168B) seem to cause watchdog
timeouts on RTL8139C+.
Introduce a new flag RL_FLAG_AUTOPAD to mark automatic padding
feature of controller and set it for RTL8139C+ and controllers that
use new descriptor format. This fixes watchdog timeouts seen on
RTL8139C+.

Reported by:	Dimitri Rodis < DimitriR <> integritasystems dot com >
Tested by:	Dimitri Rodis < DimitriR <> integritasystems dot com >
2009-04-20 07:13:04 +00:00
yongari
8224fa9318 Partial revert r185756.
It seems that RTL8168D and RTL8102EL requires additional settle
time to complete RL_PHYAR register write. Accessing RL_PHYAR
register right after the write causes errors for subsequent PHY
register accesses.

Tested by:	george at luckytele dot com,
		Steve Wills < STEVE at stevenwills dot com >
2009-03-31 03:29:05 +00:00
imp
7cf1a35509 remove now-redunant cardbus attachment lines. 2009-03-09 13:25:34 +00:00
yongari
4f064c4d72 Add a new tunable hw.re.prefer_iomap which disables memory register
mapping. The tunable is OFF for all controllers except RTL8169SC
family. RTL8169SC seems to require more magic to use memory
register mapping. r187483 added a fix for RTL8169SCe controller but
it does not looke like fix other variants of RTL8169SC.

Tested by:	Gavin Stone-Tolcher g.stone-tolcher <> its dot uq dot edu dot au
2009-03-09 06:02:55 +00:00
yongari
7c51c6c0f1 Allocating 2 MSI messages do not seem to work on certain controllers
so use just 1 MSI message. This fixes regression introduced in
r188381.

Tested by:	many
2009-02-11 00:23:56 +00:00
yongari
001e930ccf Reclaim transmitted frames in re_tick(). This is for PCIe
controllers that lose Tx completion interrupts under certain
conditions. With this change it's safe to use MSI on PCIe
controllers so enable MSI on these controllers.
2009-02-09 04:59:13 +00:00
jkim
ed18f3be3d - Add support for 8110SCe part. Some magic registers were taken from
Linux driver.
- Swap hardware revisions for 8110S and 8169S as Linux driver claims.

Reviewed by:	yongari (early version)
2009-01-20 20:22:28 +00:00
jkim
85ec29a00a Retire RL_FLAG_INVMAR bit to match its comment and reality. 2009-01-20 20:04:09 +00:00
jkim
59fb5cd35b - Do not read and write RX configuration register multiple times.
- Always program RX configuration register from scratch instead of
doing read/modify/write.
- Rename re_setmulti() to re_set_rxmode() to be reflect reality.
- Simplify hash filter logic a little while I am here.

Reviewed by:	yongari (early version)
2009-01-20 19:58:01 +00:00
yongari
ca829de633 Sometimes RTL8168B seems to take long time to access GMII registers
in device attach phase. Double GMII register access timeout value
to fix the issue.

Reported by:	wkoszek
Tested by:	wkoszek
2009-01-19 02:31:27 +00:00
yongari
38e33df2fe Since we don't request reset for rlphy(4), the link state 'UP'
event from mii(4) may not be delivered if valid link was already
established. To address the issue, check current link state after
driving MII_TICK. This should fix a regression introduced in
r185753 on fast ethernet controllers.

Reported by:	csjp, Bruce Cran < bruce <> cran DOT org DOT uk >
Tested by:	csjp, Bruce Cran (initial version)
2008-12-22 00:46:22 +00:00
yongari
62ee68bb08 It seems that RealTek PCIe controllers require an explicit Tx poll
command whenever Tx completion interrupt is raised. The Tx poll
bit is cleared when all packets waiting to be transferred have been
processed. This means the second Tx poll command can be silently
ignored as the Tx poll bit could be still active while processing
of previous Tx poll command is in progress.
To address the issue re(4) used to invoke the Tx poll command in Tx
completion handler whenever it detects there are pending packets in
TxQ. However that still does not seem to completely eliminate
watchdog timeouts seen on RealTek PCIe controllers. To fix the
issue kick Tx poll command only after Tx completion interrupt is
raised as this would indicate Tx is now idle state such that it can
accept new Tx poll command again. While here apply this workaround
for PCIe based controllers as other controllers does not seem to
have this limitation.

Tested by:	Victor Balada Diaz < victor <> bsdes DOT net >
2008-12-17 08:18:11 +00:00
yongari
4b0736516e For RTL8168C SPIN2 controllers, make sure to take the controller
out of sleep mode prior to accessing to PHY. This should fix device
attach failure seen on these controllers. Also enable the sleep
mode when device is put into sleep state.

PR:	kern/123123, kern/123053
2008-12-17 06:01:03 +00:00
yongari
73a287aa0c Make WOL work on RTL8168B. This controller seems to require
explicit command to enable Rx MAC prior to entering D3.

Tested by:	Cyrus Rahman <crahman <> gmail DOT com>
2008-12-11 02:24:11 +00:00
yongari
1dec308af8 Don't access undocumented register 0x82 on controllers that
have no such register. While here clear undocumented PHY
register 0x0B for RTL8110S.

Obtained from:	RealTek FreeBSD driver
2008-12-11 01:41:38 +00:00
yongari
5bbe456ad7 Newer RealTek controllers requires setting stop request bit to
terminate active Tx/Rx operation.
2008-12-11 01:26:18 +00:00
yongari
b23743de45 Always put controller into known state before device intialization.
While here remove re_reset calls invoked in system error case as
controller reset is always done in device initialization.
2008-12-11 00:46:07 +00:00
yongari
f630de1b0f Partly revert r185756. RTL8169SC doesn't like reduced delays in
GMII access while Tx/Rx is in progress.

Reported by:	Jaakko Heinonen <jh <> saunalahti DOT fi>,
		Anton Yuzhaninov <citrin <> citrin DOT ru>
Tested by:	Jaakko Heinonen <jh <> saunalahti DOT fi>
2008-12-11 00:30:26 +00:00
yongari
2734248c1d Reduce spin wait time consumed in GMII register access routines.
Waiting for 1ms for each GMII register access looks overkill and it
may also decrease overall performance of driver because re(4)
invokes mii_tick for every hz.

Tested by:	rpaulo
2008-12-08 02:48:41 +00:00
yongari
4130873e13 o Implemented miibus_statchg handler. It detects whether re(4)
established a valid link or not. In miibus_statchg handler add a
  check for established link is valid one for the controller(e.g.
  1000baseT is not a valid link for fastethernet controllers.)
o Added a flag RE_FLAG_FASTETHER to mark fastethernet controllers.
o Added additional check to know whether we've really encountered
  watchdog timeouts or missed Tx completion interrupts. This change
  may help to track down the cause of watchdog timeouts.
o In interrupt handler, removed a check for link state change
  interrupt. Not all controllers have the bit and re(4) did not
  rely on the event for a long time. In addition, re(4) didn't
  request the interrupt in RL_IMR register.

Tested by:	rpaulo
2008-12-08 02:34:13 +00:00
yongari
623cf60390 Make sure to return the result of meida change request.
Previously it used to return success regardless of the result.
2008-12-08 01:44:18 +00:00
yongari
98505b1380 Add 8168D support.
Submitted by:	Andrew < andrewwtulloch <> gmail DOT com >
2008-12-02 03:39:34 +00:00
yongari
6f5f8670b5 Read ethernet address from ID registers for RTL8102E/RTL8102EL as
reading from EEPROM doesn't seem to work on these controllers.

Reported by:	Milan Obuch ( freebsd-net at dino dot sk )
Tested by:	Milan Obuch ( freebsd-net at dino dot sk )
2008-09-06 00:25:16 +00:00
yongari
0fa4e4ac22 Fix VLAN hardware tag insertion/stripping on big-endian
architectures.

Reported by:	naddy
Tested on:	sparc64
MFC after:	1 week
2008-08-13 03:40:08 +00:00
yongari
bfce43df58 Rearrange conditional compilation directives. This makes syntax
highlighting work in vim.
2008-08-04 04:00:10 +00:00
yongari
f38b468cd2 Remove return keyword at the end of functions that return void. 2008-08-04 03:51:20 +00:00
yongari
62712062b0 Remove register keyword. 2008-08-04 03:47:29 +00:00
yongari
43f358fb04 Use ANSI C declarations for all functions. 2008-08-04 03:45:07 +00:00
yongari
6d9b8fb4db Don't enable TSO by default. Users of RTL8169/8110 reported
watchdog timeout issues and the root cause seems to stem from
silicon bug of controller. Personally I couldn't reproduce it on
RTL8169 controller but it seems it's dependent on usage pattern.
For newer PCIe based controllers I have no TSO complaints but
turning off TSO would be more safe. Users who are sure that
their controller works with TSO can still reenable the TSO with
ifconfig(8).

Reported by:	Oliver Lehmann (lehmann at ans-netz dot de), Eugene Butusov (ebutusov at gmail dot com)
2008-08-04 02:34:40 +00:00
yongari
a36e7d5b67 The number of bits reserved for MSS in RealTek controllers is
11bits. This limits the maximum interface MTU size in TSO case
as upper stack should not generate TCP segments with MSS greater
than the limit. Armed with this information, disable TSO if
interface MTU is greater than the limit.
2008-08-04 02:05:09 +00:00
yongari
8bced35dc2 Add driver support for RTL8102E and RTL8102EL which is the second
generation of RTL810x PCIe fast ethernet controller. Note, Tx/Rx
descriptor format is different from that of first generation of
RTL8101E series. Jumbo frame is not supported for RTL810x
family.

Tested by:	NAGATA Shinya ( maya AT negeta DOT com )
2008-07-09 01:58:18 +00:00
yongari
756491769a Disable jumbo frame support for RTL810x fast ethernet controllers. 2008-07-09 01:44:06 +00:00
yongari
991fbab98a Add a new RTL8169 variant, 8169SB(L)/8110SB(L).
Reported by:	nork
Tested by:	nork
2008-07-02 08:00:14 +00:00
yongari
739ec6bfa1 Add basic support for RTL8168C, RTL8168CP, RTL8111C and RTL8111CP.
ATM Tx/Rx checksum offload is supported but TSO and jumbo frame is
not yet supported. Because these newer controllers use different
descriptor formats, a flag RL_FLAG_DESCV2 flag was introduced to
handle that case in Tx/Rx handler. Also newer controllers seems to
require to not touch 'enable Tx/Rx bit' in RL_CPLUS_CMD register
so don't blindly try to set that bits.

Note, it seems that there is still power-saving related issue where
driver fails to attach PHY. Rebooting seems to fix that issue but
number of required reboots varys.

Many thanks to users that helped during developement. I really
appreciate their patient and test/feedbacks.
2008-07-02 07:54:53 +00:00
yongari
44c668905b Display detected chip revision in device attach. This will help to
diagnose revision specific issues in future. Also add 0x to notify
that the revision number is in hex form.
2008-07-02 06:55:03 +00:00
yongari
b2a4327b82 If MSI is not active make sure to disable MSI in EEPROM. 2008-07-02 06:45:59 +00:00
yongari
b32906b68f In device detach don't access ifnet structure unless device is
attached. This fixes NULL pointer dereference when polling(9) is
active and unsupported hardware is detected in device attach.
2008-07-02 06:41:46 +00:00
yongari
7238fff022 Toggling IFF_ALLMULTI flag does not require full interface
reintialization.
2008-07-02 06:34:02 +00:00
yongari
84387bd2a3 Instead of allocating variables for each events/hardware flags, use
a dedicated flag that represents controller capabilities/events.
This will simplify many part of code that requires different
workaround for each controller revisions and will enhance
readability.
While I'm here move PHY wakeup code up before mii_phy_probe() which
seems to help to wake PHY in some cases.
2008-07-02 06:29:43 +00:00
yongari
31d44ce02d Switch to memory space register mapping over IO space. If that
mapping fails fall back to traditional IO space access.
2008-07-02 05:21:09 +00:00
yongari
124e2b3fa0 While accessing EEPROM command register use pre-defined constant
instead of hardcoded value.
2008-07-02 05:01:19 +00:00
yongari
241b812829 After the change of r176757 re(4) no longer relys on reading
RL_TXCFG register to identify a device in device probe. Reflect the
fact by modifing device description with general ethernet
controller family.
Note, rl_basetype in struct rl_type is not used and the more
detailed information is provided with rl_hwrev structure.
2008-07-02 04:55:39 +00:00
yongari
9ceaa3abd6 Remove duplicated H/W revision check. 2008-07-02 04:27:36 +00:00
yongari
8d7bbd176a Don't touch MSI enable bit in RL_CFG2 register. For unknown reason
clearing MSI enable bit for MSI capable hardwares resulted in Tx
problems. MSI enable bit is set only when MSI is requested from
user.

Tested by:	remko
2008-04-15 00:46:15 +00:00
yongari
55186b0e36 Padding more bytes than necessary one broke another variants of
PCIe RealTek chips. Only pad IP packets if the payload is less than
28 bytes.

Obtained from:	NetBSD
PR:		kern/122221
2008-03-31 04:03:14 +00:00
yongari
e8dec714c1 In revision 1.70, 1.71 and 1.84 re(4) tried to workaround checksum
offload bugs by manual padding for short IP/UDP frames. Unfortunately
it seems that these workaround does not work reliably on newer PCIe
variants of RealTek chips.

To workaround the hardware bug, always pad short frames if Tx IP
checksum offload is requested. It seems that the hardware has a
bug in IP checksum offload handling. NetBSD manually pads short
frames only when the length of IP frame is less than 28 bytes but I
chose 60 bytes to safety. Also unconditionally set IP checksum
offload bit in Tx descriptor if any TCP or UDP checksum offload is
requested. This is the same way as Linux does but it's not
mentioned in data sheet.

Obtained from:	NetBSD
Tested by:	remko, danger
2008-03-28 01:21:21 +00:00
yongari
fcd39263e4 MSI handling on some RealTek chips are broken so disable it by
default.

Reported by:	Giulio Ferro ( auryn AT zirakzigil DOT org )
Tested by:	Giulio Ferro ( auryn AT zirakzigil DOT org )
2008-03-23 05:35:18 +00:00