Commit Graph

83 Commits

Author SHA1 Message Date
adrian
86c6170821 [mdio] migrate mdiobus out of etherswitch and into a top-level device of its own.
The mdio driver interface is generally useful for devices that require
MDIO without the full MII bus interface. This lifts the driver/interface
out of etherswitch(4), and adds a mdio(4) man page.

Submitted by:	Landon Fuller <landon@landonf.org>
Differential Revision:	https://reviews.freebsd.org/D4606
2015-12-26 02:31:39 +00:00
adrian
434ff9cdd9 [arswitch] bump the number of ports on the ar934x internal switch.
It indeed has more ports by default.
2015-12-15 04:46:48 +00:00
zbb
6644b9d363 Introduce e6000sw etherswitch support
Add e6000sw driver supporting Marvell 88E6352, 88E6172, 88E6176 switches.
It needs to be attached to mdio interface, exporting SMI access
functionality. e6000sw supports port-based VLAN configuration, per-port
media changing, accessing PHY and switch registers.

e6000sw attaches miibuses and PHY drivers as children. Instead of typical
tick as callout, kthread-based tick is used. This combined with SX locks
allows MDIO read/write calls to sleep. It is expected, because this
hardware requires long delays in SMI read/write procedures, which can not
be handled by busy-waiting.

Reviewed by:    adrian
Obtained from:  Semihalf
Submitted by:   Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D3902
2015-10-25 22:14:04 +00:00
adrian
4f765a9a46 AR8327: Fix up the ability to configure the vlangroup configuration for the CPU port
I messed up when doing the reset_vlans method - setting vid[0] = 1 here
was making it 'hidden' from configuration (as it needed ETHERSWITCH_VID_VALID
as well) and so there was no way to configure vlangroup0.

In per-port VLAN mode, vlangroup0 is for the CPU port (port0).
Now, it normally wouldn't really matter - the CPU port thus sees
all other ports. However there are two CPU ports on the AR8327 and
so port0 (arge0) was seeing all traffic on port6 (arge1).
If you thus tried to use arge1/port6 for anything (eg a WAN port)
in a bridge group then things would very upset very quickly.

Whilst here, add a comment to remind myself that yes, it'd be nice
if we could specify a boot-time switch config.

Tested:

* AP135 reference platform w/ AR8327N switch
2015-10-20 21:18:02 +00:00
rpaulo
18ba5caedb Fix French typos in etherswitch. 2015-04-18 07:34:39 +00:00
adrian
f1ee7f6d79 Turns out the AR933x looks like the AR7240/AR7241 switch as far as VLAN
configuration is concerned.

So, remove the now-erroneous comment.

Tested:

* AR9331 - Carambola2, with transmitting dot1q tagged packets around.
2015-03-28 23:20:46 +00:00
adrian
6cfab9d9d9 Commit 802.1q configuration support for the AR8327.
This is slightly different to the other switches - the VLAN table
(VTU) programs in the vlan port mapping /and/ the port config
(tagged, untagged, passthrough, any.)

So:

* Add VTU operations to program the VTU (vlan table)
* abstract out the mirror-disable function so it's .. well, a function.
* setup the port to have a dot1q configuration for dot1q - the
  port security is VLAN (not per-port VLAN) and requires an entry
  in the VLAN table;
* add set_dot1q / get_dot1q to program the VLAN table;
* since the tagged/untagged ports are now programmed into the VTU,
  rather than global - plumb the ports /and/ untagged ports bitmaps
  through the arswitch API.

Tested:

* AP135 - QCA9558 SoC + AR8327N switch
2015-03-13 02:16:39 +00:00
adrian
986216c4aa Methodise a couple more of the VLAN methods. 2015-03-08 23:02:15 +00:00
adrian
64169d7b6b Add per-port vlan support for the AR8327.
All the per-port support is really doing is applying a port visibility
mask to each of the switchports.  Everything still look like a single
portgroup (vlan id 1), but the per-port visibility mask is modified.

Whilst I'm here, also add some initial dot1q support - the pvid stuff
is doing the right thing, but it's not useful without the rest of
the VLAN table programming.

It's enough for me to be able to use the LAN/WAN port distinction
on the AP135, where there isn't (for now!) a dedicated PHY for the
"WAN" port.

Tested:

* AP135, QCA9558 SoC + AR8327 switch
2015-03-08 21:59:03 +00:00
adrian
eb84aa9453 Fix up support for the AR8327.
* Even though I got the registers around "right", it seems
  I'm not tickling the MDIO access correctly for the internal PHY
  bus.  Some of the switches are fine poking at the external PHY
  registers; others aren't.  So, enable direct PHY bus access
  for the AR8327, and leave the existing code in place for the
  others.

* Go and shuffle the register access around.  Whilst here,
  restore the 2ms delay if changing page.

* Comment out some of the stub printf()s; there's some upcoming
  work to add port VLAN support.

Tested:

* AP135 development board
* Carambola2 - AR9331 SoC
2015-03-08 03:53:36 +00:00
adrian
f847122d9d AR8327: Disable energy-efficient ethernet support in the PHYs.
I noticed that openwrt/linux does this, citing "instability", so
until they figure out why I'm going to disable it here as well.

Tested:

* QCA AP135 - QCA955x SoC + AR8327 switch.
2015-03-01 20:32:35 +00:00
adrian
a4584a056f Bump the port mask on the AR8327 ethernet switch from 0x3f to 0x7f.
So, it turns out that the AR8327 has 7 ports internally:

* GMAC0 / external (CPU) MAC0
* GMAC1 / port1 -> GMAC5 / port5: external switch port PHYs
* GMAC6 / external (CPU) MAC1

Now, depending upon how things are wired up, the second CPU port (MAC1)
can be wired to either the switch (port6), or through port5's PHY, bypassing
the GMAC+switch entirely.  Ie, it can pretend to be a boring PHY, saving
system designers from having to include a separate PHY for a "WAN" port.

Here's the rub - the AP135 board (QCA955x SoC) hooks up arge0 to
the second CPU port on the AR8327, but it's hooked up as RGMII.
So, in order to hook it up to the rest of the switch, it isn't configured
as a separate PHY - OpenWRT has it setup as connected via RGMII to
GMAC6 and (I'm guessing) it's set to be a WAN port by configuring up
port-based VLANs or something.

Thus, with a port mask of 0x3f, GMAC6 was never allowed to receive traffic
from any other port.  It could transmit fine, but not receive anything.

So, now it works enough for me to continue doing board bootstrapping.
Note, this isn't enough to make the QCA955x + AR8327 work - there's
a bunch of uncommitted work to both the platform SoC (interrupt handling,
ethernet, etc) and the ethernet switch (register access space, setup, etc)
that needs to happen.  However, this particular change is also relevant to
other SoCs, like the AR934x and AR7161, both of which can be glued to
this switch.

Tested:

* AP135 development board

TODO:

* Figure out whether I can somehow abuse another port mode to have this
  be a pass-through PHY, or whether I should just create some more boot
  time hints to explicitly set up port-based isolation so this works
  in a more useful way by default.
2015-03-01 20:22:28 +00:00
adrian
0227065711 Add another register definition for the AR8327.
Obtained from:	OpenWRT
2015-02-28 23:59:29 +00:00
adrian
520bf5b954 Add another revision of the AR8327. 2014-07-26 21:33:17 +00:00
rpaulo
fa4a56f30b Revert r268543.
We should probably fix sys/gpio.h instead.
2014-07-12 06:23:42 +00:00
rpaulo
94e9ac2125 Move iic.h to sys/ so that it's automatically installed in /usr/include/sys.
This lets us call iic(4) ioctls without needing the kernel source code
and follows the same model of GPIO.

MFC after:	3 weeks
2014-07-12 01:04:10 +00:00
loos
d4ce3e7614 Allow the PVID setting on CPU port.
Return our static list of supported media for the CPU port.

Tested on TP-Link 1043ND.
2014-07-05 19:31:22 +00:00
loos
96e0511f76 Initialize the switch vlan table at attachment.
Update some comments on code, specifying the correct vlans used on switch
setup.

Advertise the proper switch operation mode (the rtl8366rb only support
dot1q vlans).

This fixes the breakage that i introduced on r249752 and make the rtl8366rb
switch works again with etherswitchcfg(8).

Tested on TP-Link 1043ND.

Tested by:	me, Harm Weites (harm at weites.com)
2014-07-03 19:50:50 +00:00
loos
6ca4962ff1 Fix the reported status for the switch CPU port which was (wrongly)
reporting half-duplex link.

Tested on TP-Link WR1043ND.
2014-07-01 14:49:46 +00:00
loos
2c297e6c2d Add the CPU port flag to the CPU port on rtl8366 (port 5).
Do not allow any media change on the switch CPU port.

Tested on TP-Link WR1043ND.
2014-07-01 14:33:48 +00:00
loos
e52a56067a Fix the build with debug enabled and remove a variable used only at switch
initialization, it is nonsense keep it around without futher use.
2014-05-09 13:21:34 +00:00
loos
ff041b946c Fix a bug on ip17x switch initialization which will fail as soon as you
disable the debug and diagnosis options from current.  We must wait 2ms
after the switch reset and not 2us.

Tested on RB433UAH.
2014-05-09 13:07:39 +00:00
adrian
e27a461d5d Add a description here. 2014-03-02 07:39:37 +00:00
adrian
e85950412d Set all of the ports into the same vlangroup; there's only one vlangroup
(pvid=1) and we already configure them to send to other ports.

Setting pvid=portnum would mean that there were separate vlangroups
for each ports, but 'leaking' into other ports.  The result? All port
traffic flooded to all other port traffic.

Tested:

* DB120, AR9344 + AR8327 switch
2014-03-02 07:10:43 +00:00
adrian
6ec7b630f8 Add ATU flush support.
The OpenWRT AR8xxx switch support flushes the ATU (address translation
unit) after each port link 'up' status change.  I've modified this to
just flush on any port transition.

Whilst here, bump the number of ports on the AR8327 to 6, rather than
the default of 5.  It's DB120 specific; I'll go and make this configurable
later.

There's some debugging code in here still; I am still debugging whether
this is or isn't working fully.

Tested:

* DB120, AR9344 + AR8327 switch

Obtained from:	OpenWRT
2014-03-02 05:48:56 +00:00
adrian
c16798be43 Add AR8216 era ATU management/configuration register definitions.
Obtained from:	OpenWRT
2014-03-02 05:47:05 +00:00
adrian
263a450392 (I think!) make the AR8327 switch correctly handle traffic.
This patch does four things:

* it globally disables mirroring;
* it globally sets the mirroring on each port to be disabled;
* the initial port setup now programs a portmask for the port to allow
  transmission (forwarding) to all other ports bar itself;
* the vlan setup path now programs the portmask for the port to
  allow transmission (forwarding) to all other ports bar itself.

Before this, I hard-coded the portmask to 0x3f which would mean all
ports (bar port 6, which currently isn't hooked up to anything.)
This means that traffic would be duplicated back out the port it
received it.  I bet this wasn't .. optimal.

In any case, this _seems_ to make DHCP from my macosx laptop
work through this access point.  I'll do some further testing
to ensure it's actually working correctly on all my devices.

Tested:

* DB120, AR8327 switch
2014-03-01 10:04:31 +00:00
adrian
1bfee5ea6c Be paranoid about bit operations here. 2014-03-01 00:11:45 +00:00
adrian
9053a4bf3c Remove now dead code. 2014-03-01 00:02:09 +00:00
brueffer
9f063680a1 Add missing includes and remove two unused ones.
Reviewed by:	loos
MFC after:	1 week
2014-02-27 21:01:10 +00:00
adrian
779dd49fe3 Add LED setup support for the AR8327.
Tested:

* DB120

Obtained from:	OpenWRT
2014-02-26 02:00:37 +00:00
adrian
0c615557a0 Add in the SGMII configuration code. The DB120 doesn't use it, so I
have no way to evaluate it.

Obtained from:	OpenWRT
2014-02-26 01:46:42 +00:00
adrian
f36113a5f9 Undo the DB120 hard-coded values in the AR8327 code and fetch it from
the hints environment.

Tested:

* DB120
2014-02-26 01:32:06 +00:00
adrian
4578386a6e Add in port0/port6 configuration as part of the platform data code path.
It's still hardcoded (for db120) but it is now hardcoded in all the
same place (ie, the pdata path.)  The port config/status code now checks
port0/port6 as appropriate to configure things.

Tested:

* Qualcomm Atheros DB120, AR8327 switch.
2014-02-24 05:55:00 +00:00
adrian
c03f7499ea Link the AR8327 to the build. 2014-02-24 04:47:27 +00:00
adrian
14d0aacff0 Add initial AR8327 support.
This is (almost!) enough to actually probe, attach, configure a default
port group and do some basic work.  It's also totally hard-coded for
the Qualcomm Atheros DB120 board - it doesn't yet have any of the code
from OpenWRT which parses extra configuration data to know how to program
the switch.  The LED stuff is also missing.

But, it's enough to facilitate board, PHY, switch and VLAN bringup,
so I am committing it now.

Tested:

* Qualcomm Atheros DB120

Obtained from:	OpenWRT
2014-02-24 04:47:16 +00:00
adrian
51961034e3 Methodize the arswitch VLAN routines.
These differ per chipset family in subtle and evil ways.

It becomes very noticable on the AR8327 where the layout is just plain
wrong.
2014-02-24 04:44:28 +00:00
adrian
05b5deca74 * Ensure enough ports/phys are available for both the AR8327 and previous
switches.

* Add some new VLAN HAL methods that will be used by the VLAN configuration
  code.  The AR933x and later switches use slightly different register
  layouts (even though the driver currently doesn't support it.)
2014-02-24 04:43:23 +00:00
adrian
a4be223241 Extract out the port VLAN flags/setup code and throw it into two new
HAL methods.

This allows the AR8327 code to override it as appropriate.

Tested:

* DB120 - AR8327 and AR9340 on-board switch; only running 'etherswitchcfg'
  to check configs.  The actual VLAN programming wasn't tested.
2014-02-19 06:43:52 +00:00
adrian
d45e8830ab Add methods for the VLAN port set/get routines.
The registers (and perhaps the flags) are different for the AR8327, so
I'll stub those out until they're written.

Tested:

* DB120 - both on-chip AR9340 and AR8327 switches.
2014-02-19 06:35:17 +00:00
adrian
472a51527b Turn the port init function into a HAL method and initialise it to the
default port init code.

This needs to be overridden for the AR8327.
2014-02-19 06:03:58 +00:00
adrian
32733ba485 Teach the PHY register path about the different MDIO bus address
for the AR8327.

Tested:

* AR8327, DB120
2014-02-19 06:02:47 +00:00
adrian
135fe0a255 Add a new method to set up the individual port in question.
The AR8327 requires some different setup code.
2014-02-19 06:01:40 +00:00
adrian
af3c3253f5 Change arswitch_ports_init() to arswitch_port_init(), and teach it to take
a single port to setup.

This may end up later being used as part of some logic to program
the PHY for a single port, rather than having to reinitialise them
all at once.

Tested:

* DB120
2014-02-19 05:35:41 +00:00
adrian
f0624d1188 Add in the AR8327 probe/attach code and switch type.
It detects fine, but (as expected) it won't attach just yet, let alone
pass traffic.

Tested:

* DB120, AR8327 switch
2014-02-19 05:09:47 +00:00
adrian
4223f4f321 Store away the chip version and revision; some AR8327 code depends upon
the chip revision.
2014-02-19 04:30:53 +00:00
adrian
d6af13f80d Add in a flag to control whether the low or high data word of a register access
is latched in first.

The AR8327 apparently requires the low data word be latched in first.

Obtained from:	Linux OpenWRT
2014-02-19 04:23:01 +00:00
adrian
6aa41da310 The MDIO control register for the AR8327 has a different address to
previous chipsets.

Obtained from:	AR8327 datasheet
2014-02-17 05:54:24 +00:00
adrian
d2f35ec8a2 Add mmd declaration. 2014-02-17 05:51:37 +00:00
adrian
56a90dfc6e Implement PHY bus MMD writes for arswitch.
This is used by the AR8327 PHY setup path.

Obtained from:	OpenWRT
2014-02-17 02:24:58 +00:00